TCA6424 Datasheet, PDF (12/29 Pages) Texas Instruments – LOW-VOLTAGE 24-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

TCA6424
LOW-VOLTAGE 24-BIT I²C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS175 – NOVEMBER 2007
www.ti.com
Slave Address
Acknowledge
From Slave
Acknowledge
From Slave
Slave Address
Acknowledge
From Slave
Data From Lower
or Upper Byte _Acknowledge
of Register _{From Master}
S
0
1
0
0
0
1
AD
DR
0
A
R/W
Command Byte
A
S
0
1
0
0
0
1
AD
DR
1
A MSB
Data
LSB A
At this moment, master transmitter
R/W
becomes master receiver, and
slave receiver becomes slave transmitter.
First Byte
Data From Upper
or Lower Byte No Acknowledge
of Register
From Master
Figure 8. Read From Register
MSB
Data
Last Byte
LSB NA P
<br/>
SCL
123456789
I0.x
SDA
S
0
1
0
0
0
1
AD
DR
1
A
Data 1
Read From
Port 0
Data Into
Port 0
Read From
Port 1
Data Into
Port 1
INT
Read From
Port 2
Data Into
Port 2
R/W Acknowledge
From Slave
t_iv
t_ir
I1.x
A
Data 2
Acknowledge
From Master
I2.x
A
Data 3
Acknowledge
From Master
I0.x
A
Data 4
1P
Acknowledge
From Master
No Acknowledge
From Master
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port (see Figure 8).
C. Auto-increment mode is enabled.
Figure 9. Read Input Port Register
12
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