SLK2501 Datasheet, PDF (6/20 Pages) Texas Instruments – OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLK2501
OCĆ48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER
SLLS502A – OCTOBER 2001 – REVISED NOVEMBER 2001
Terminal Functions(Continued)
control/status pins (continued)
TERMINAL
NAME
NO.
PRBSPASS
42
TYPE
TTL output
PAR_VALID
SPILL
2 TTL output
49 TTL output
DESCRIPTION
PRBS test result. This pin reports the status of the PRBS test results (High = pass).
When PRBSEN is disabled, the PRBSPASS pin is set low. When PRBSEN is enabled
and a valid PRBS is received, then the PRBSPASS pin is set high.
Parity checker output. The internal parity checker on the parallel side of the transmitter
checks for even parity. If there is a parity error, the pin is pulsed low for two clock cycles.
TX FIFO collision output
voltage supply and reserved pins
TERMINAL
NAME
NO.
VDDLVDS
62, 72, 75, 78,
90, 91, 92, 97
GNDLVDS 61, 69, 76, 77,
89, 93, 96, 100
VDD
3, 22, 25, 29,
32, 35, 50
GND
1, 6, 19, 23, 26,
28, 30, 31, 33,
40
VDDA
7, 16
GNDA
10, 13
VDDPLL
11
GNDPLL
12
RSVD
52
TYPE
Supply
Ground
Supply
Ground
Supply
Ground
Supply
Supply
Reserved
LVDS supply voltage (2.5 V)
LVDS ground
Digital logic supply voltage (2.5 V)
Digital logic ground
DESCRIPTION
Analog voltage supply (2.5 V)
Analog ground
PLL voltage supply (2.5 V)
PLL ground
This pin needs to be tied to ground or left floating for normal operation.
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