SLK2501 Datasheet, PDF (14/20 Pages) Texas Instruments – OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLK2501
OCĆ48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER
SLLS502A – OCTOBER 2001 – REVISED NOVEMBER 2001
electrical characteristics over recommended operating conditions (unless otherwise noted)
TTL
VIH
VIL
IIH
IIL
VOH
VOL
CI
PARAMETER
High-level input voltage
Low-level input voltage
Input high current
Input low current
High-level output voltage
Low-level output voltage
Input capacitance
LVDS input signals
PARAMETER
VI
VID(th)
CI
RI
tsu
th
T(duty)
Input voltage
Input differential threshold voltage
Input capacitance
Input differential impedance
Input setup time requirement
Input hold time requirement
Input clock duty cycle
LVDS output signals
PARAMETER
VOD
VOS
∆VOD
∆VOS
I(SP), I(SN),
I(SPN)
Ioff
t(cq_min)
t(cq_max)
tr/tf
Output differential voltage
Output common mode voltage
Change VOD between 1 and 0
Change VOS between 1 and 0
Output short circuit current
Power-off current
Clock-output time
Output transition time
Output clock duty cycle
Data output to FRAME_SYNC delay
TEST CONDITIONS
VDD = MAX,
VDD = MAX,
IOH = –1 mA
IOH = 1 mA
VIN = 2 V
VIN = 4 V
TEST CONDITIONS
On-chip termination
See Figure 8
See Figure 8
TEST CONDITIONS
RL = 100 ±1%
Outputs shorted to ground or shorted together
VDD = 0 V
See Figure 7
20%to80%
MIN
2
–40
2.10
MIN
825
100
80
300
300
40%
MIN
300
1070
100
45%
4
TYP MAX UNIT
3.6 V
0.80 V
40 µA
µA
2.3
V
0.25 0.5 V
4 pF
TYP MAX UNIT
1575 mV
mV
3 pF
100 120 Ω
ps
ps
60%
TYP MAX UNIT
800
1375
mV
25
25
24 mA
10
100
100
300
55%
7
µA
ps
ps
Bit
times
timing requirements over recommended operating conditions (unless otherwise noted)
reference clock (REFCLK)
PARAMETER
Frequency tolerance^†
TEST CONDITIONS MIN
–20
TYP MAX UNIT
20 ppm
Duty cycle
40% 50% 60%
Jitter
12 kHz to 20 MHz
3 ps rms
Frequency range absolute value
622.08
MHz
† _{The ±20 ppm tolerance is required to meet SONET/SDH requirements. For non-SONET/SDH compliant systems, looser tolerances may apply.}
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