SLK2501 Datasheet, PDF (4/20 Pages) Texas Instruments – OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLK2501
OCĆ48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER
SLLS502A – OCTOBER 2001 – REVISED NOVEMBER 2001
Terminal Functions
clock pins
TERMINAL
NAME
NO.
REFCLKP,
94
REFCLKN
95
TXCLKP,
79
TXCLKN
80
TXCLKSRCP, 70
TXCLKSRCN
71
RXCLKP,
67
RXCLKN
68
TYPE
DESCRIPTION
LVDS/PECL
compatible input
LVDS input
Differential reference input clock. There is an on-chip 100-Ω termination resistor differentially
placed between REFCLKP and REFCLKN. The dc bias is also provided on-chip for ac-coupled
case.
Transmit data clock. The data on TXDATA(0:3) is latched on the rising edge of TXCLKP.
LVDS output
LVDS output
Transmit clock source. A clock source generated from the SLK2501 to the downstream device
(i.e., framer) that could be used by the downstream device to transmit data back to the SLK2501.
This clock is frequency-locked to the local reference clock.
Receive data clock. The data on RXDATA(0:3) is on the falling edges of RXCLKP. The interface
of RXDATA(0:3) and RXCLKP is source synchronous (refer to Figure 7).
serial side data pins
TERMINAL
NAME
NO.
STXDOP,
9
STXDON
8
SRXDIP,
14
SRXDIN
15
TYPE
DESCRIPTION
PECL compatible
output
PECL compatible
input
Transmit differential pairs; high speed serial outputs.
Receive differential pairs; high speed serial inputs.
parallel side data pins
TERMINAL
NAME
NO.
TYPE
TXDATA[0:3]
P/N
88–81 LVDS input
TXPARP,
TXPARN
99 LVDS input
98
RXDATA[0:3] 66–63, LVDS output
P/N
60–57
DESCRIPTION
Transmit data pins. Parallel data on this bus is clocked on the rising edge of TXCLKP.
TXDATA0 is the first bit transmitted in time.
Transmit data parity input
Receive data pins. Parallel data on this bus is valid on the falling edge of RXCLKP (refer to
Figure 7). RXDATA0 is the first bit received in time.
RXPARP,
RXPARN
FSYNCP,
FSYNCN
56 LVDS output
55
73 LVDS output
74
Receive data parity output
Frame sync pulse. This signal indicates the frame boundaries of the incoming data stream. If the
frame-detect circuit is enabled, FSYNC pulses for four RXCLKP and RXCLKN clock cycles,
when it detects the framing patterns.
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