DDC316 Datasheet, PDF (6/24 Pages) Texas Instruments – 16-Channel, Current-Input Analog-to-Digital Converter

DDC316
SBAS370 – MARCH 2008 .................................................................................................................................................................................................. www.ti.com
TIMING DIAGRAMS
CLK
CONV
DVALID
DIN
DCLK
DOUT⁽¹⁾
t_CLK
t_MEAS
t_INTA
t_CLKPW
t_CLKPW
t_DCDV
t_DVDO
MSB
t_DIDC
t_DOHD
t_DCDI
t_CNDC
t_DOPD
LSB
t_CNDC
t_INTB
t_DCLKPW
t_DCLKPW
t_DCLK
Side B Data
NOTE: (1) DOUT1 in TDM data output mode; DOUT1 through DOUT4 in parallel data output mode.
Figure 1. Serial Interface Timing
Side A Data
TIMING REQUIREMENTS FOR Figure 1
At T_A = 0°C to +70°C and DVDD = 3V to 3.6V, unless otherwise noted.
SYMBOL
DESCRIPTION
MIN
t_CLK
CLK period (1/f_CLK)
25
t_CLKPW CLK pulse width, positive or negative
0.4
HI_SPEED bit = 0
400
HI_SPEED bit = 0, CLK = 40MHz
10
t_INTA,B
Integration time for sides A and B
HI_SPEED bit = 1
800
HI_SPEED bit = 1, CLK = 40MHz
20
t_MEAS
Time required to perform
measurement
HI_SPEED bit = 0
HI_SPEED bit = 1
t_DIDC
Setup time from DIN to rising edge of DCLK
2
t_DCDI
Hold time for DIN after rising edge of DCLK
0
t_DVDO(1) Falling edge of DVALID to valid DOUT
t_DCDV(1) Falling edge of first DCLK to rising edge of DVALID
t_DCLK
DCLK period (1/f_DCLK)
25
t_DCLKPW DCLK pulse width, positive or negative
0.4
t_DOPD(1) Propogation delay from the falling edge of DCLK to valid DOUT1
t_DOHD ⁽¹⁾
Hold time during which previous DOUT1 is valid after falling edge of
DCLK
5
t_CNDC Time between CONV toggle and data retreival
5
(1) Output load = 100kΩ || 10pF
TYP
274
544
6
19
MAX
1000
1000
25
40,000
1000
10
21
UNIT
ns
t_CLK periods
t_CLK periods
µs
t_CLK periods
µs
t_CLK periods
t_CLK periods
ns
ns
ns
ns
ns
t_DCLK periods
ns
ns
ns
6
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