DDC316 Datasheet, PDF (11/24 Pages) Texas Instruments – 16-Channel, Current-Input Analog-to-Digital Converter

DDC316
www.ti.com .................................................................................................................................................................................................. SBAS370 – MARCH 2008
Figure 7 shows the block diagrams of the five states
of the front end integrator. The conversion starts with
the integrator being configured as shown in
Figure 7a. In this state, the ADC converts the
integrated value of side A of the previous phase.
Once the conversion is done, the integrator waits until
the ADC finishes converting the other three integrated
values (Figure 7b). At the completion of all four A/D
conversions, the charge on the integrator capacitor
(C_F) is reset with S_REF and S_RESET (see Figure 7c). In
this manner, the selected capacitor is charged to the
reference voltage, VREF. Once the integration
capacitor is charged, S_REF and S_RESET are switched
so that VREF is no longer connected to the amplifier
circuit while it waits to begin integrating (see
Figure 7d). With the rising edge of CONV, S_INTA
closes, which begins the integration of side A. This
process puts the integrator stage into Integrate mode
(see Figure 7e).
Charge from the input signal is collected on the
integration capacitor, causing the voltage output of
the amplifier to decrease. The falling edge of CONV
stops the integration by switching the input signal
from side A to side B (S_INTA and S_INTB). Before the
falling edge of CONV, the signal on side B was
converted by the ADC and reset during the time that
side A was integrating. With the falling edge of
CONV, side B starts integrating the input signal. At
this point, the output voltage of the side A operational
amplifier is presented to the input of the ADC, and
the entire cycle repeats.
This internal switching network is controlled externally
with the convert pin (CONV) and the system clock
(CLK). For the best noise performance, CONV must
be synchronized with the rising edge of CLK. It is
recommended that CONV toggle within ±5ns of the
rising edge of CLK. The noninverting inputs of the
integrators are connected to ground. Consequently,
the DDC316 analog ground should be as clean as
possible.
S_INT
IN
S_RESET
C_F
S_REF
VREF
S_REF
S_ADC
To
Converter
S_INT
IN
S_RESET
C_F
S_REF
VREF
S_REF
S_ADC
To
Converter
a) Convert Configuration
S_INT
IN
S_RESET
C_F
S_REF
VREF
S_REF
S_ADC
To
Converter
b) Wait to Reset Configuration
S_INT
IN
S_RESET
C_F
S_REF
VREF
S_REF
S_ADC
To
Converter
c) Reset Configuration
S_INT
IN
S_RESET
d) Wait to Integrate Configuration
C_F
S_REF
VREF
S_REF
S_ADC
To
Converter
e) Integrate Configuration
Figure 7. Diagrams for the Five Configurations of DDC316 Front-End Integrators
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