DDC316 Datasheet, PDF (12/24 Pages) Texas Instruments – 16-Channel, Current-Input Analog-to-Digital Converter

DDC316
SBAS370 – MARCH 2008 .................................................................................................................................................................................................. www.ti.com
FREQUENCY RESPONSE
The frequency response of the DDC316 is set by the
front-end integrators and is consistent with a
traditional continuous time integrator, as shown in
Figure 8. By adjusting t_INT, the user can change the
3dB bandwidth and the location of the notches in the
response. The frequency response of the ADC that
follows the front-end integrator is of no consequence
because the converter samples a held signal from the
integrators. That is, the input to the ADC is always a
DC signal. Aliasing can occur because the output of
the front-end integrators are sampled. Whenever the
frequency of the input signal exceeds one-half of the
sampling rate, the signal folds back down to lower
frequencies.
0
-10
-20
-30
-40
-50
0.1
1
10
100
t_INT
t_INT
t_INT
t_INT
Frequency
Figure 8. DDC316 Frequency Response
Ranges
There are three different capacitors available on-chip
for both sides of every channel in the DDC316. The
range control bits (Range[1:0]) change the capacitor
value for all integrators. Consequently, all inputs and
both sides of each input always have the same
full-scale (FS) range. Table 1 shows the capacitor
value selected for each range selection.
RANGE
1
2
3
Table 1. Range Selection
RANGE[1:0]
BITS
00
01
10
C_F
(pF, typ)
0.75
1.5
3
INPUT RANGE
(pC, typ)
–0.0469 to 3
–0.0938 to 6
–0.1876 to 12
Resolution
The DDC316 provides three different resolutions for
the convenience of the user. The user can select the
resolution needed for the application and the time
available for data retrieval. The three available
resolutions are 16-bit, 14-bit, and 12-bit. The serial
output data from the DDC316 are provided in an
offset binary code, as shown in Table 2. The RES
bits in the configuration register select how many bits
are used in the output word. When 12-bits are
selected, the last four bits are truncated; when 14-bits
are chosen, the last two bits are truncated. Note that
an offset is included in the output to allow slightly
negative inputs (for example, from board leakages)
from clipping the reading. The offset is approximately
1.8% of the positive full-scale.
OPERATION SETTINGS
The DDC316 provides different settings of operation
to provide flexibility in terms of range, resolution, etc.
The settings are programmable using an on-chip
register and are described in the following sections.
Data Format
The DDC316 outputs 12 to 16 bits of data depending
on the selected resolution. The format is straight
binary with an offset to help prevent leakage currents
from the printed circuit board (PCB), or the sensors
forcing a clipping on the negative full-scale. Table 2
summarizes the ideal output codes for the different
resolutions.
Table 2. Ideal Output Code⁽¹⁾ vs Input Signal
INPUT
SIGNAL
≥ 100% FS
0.07019% FS
0.02136% FS
0.00305% FS
0.001525% FS
0% FS
–1.7857% FS
IDEAL OUTPUT CODE
RESOLUTION = 16 BITS
1111 1111 1111 1111
0000 0100 1100 0000
0000 0100 1010 0000
0000 0100 1001 0100
0000 0100 1001 0011
0000 0100 1001 0010
0000 0000 0000 0000
IDEAL OUTPUT CODE
RESOLUTION = 14 BITS
1111 1111 1111 11
0000 0100 1100 00
0000 0100 1010 00
0000 0100 1001 01
0000 0100 1001 00
0000 0100 1001 00
0000 0000 0000 00
(1) Excludes the effects of noise, INL, offset, and gain errors.
IDEAL OUTPUT CODE
RESOLUTION = 12 BITS
1111 1111 1111
0000 0100 1100
0000 0100 1010
0000 0100 1001
0000 0100 1001
0000 0100 1001
0000 0000 0000
12
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