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| CD74HC4024 Datasheet, PDF (6/7 Pages) Texas Instruments – High Speed CMOS Logic 7-Stage Binary Ripple Counter | |||
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CD74HC4024, CD74HCT4024
Switching Speciï¬cations Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
SYMBOL CONDITIONS (V)
25oC
-40oC TO 85oC -55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
Output Transition
tTLH, tTHL CL = 50pF
Input Capacitance
CIN CL =15pF
Power Dissipation Capacitance CPD CL =15pF
(Notes 4, 5)
4.5
-
-
15
-
19
-
22
ns
-
-
-
10
-
10
-
10
pF
5
-
30
-
-
-
-
-
pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per package.
5. PD = VCC2 fi + â (CLVCC2 fi/M) where: M = 21, 22, 23, 24,25, 26, 27 fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply
Voltage.
Test Circuits and Waveforms
trCL
CLOCK
90%
10%
tfCL
50%
10%
tWL
tWL
+
tWH
=
I
fCL
50%
50%
tWH
VCC
GND
trCL = 6ns
CLOCK
2.7V
0.3V
tfCL = 6ns
tWL
+
tWH
=
I
fCL
3V
1.3V
0.3V
1.3V
1.3V
GND
tWL
tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
tr = 6ns
INPUT
tTHL
2.7V
1.3V
0.3V
INVERTING
OUTPUT
tPHL
tf = 6ns
3V
GND
tTLH
90%
1.3V
10%
tPLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6
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