CD74HC4024 Datasheet, PDF (5/7 Pages) Texas Instruments – High Speed CMOS Logic 7-Stage Binary Ripple Counter

CD74HC4024, CD74HCT4024
Prerequisite for Switching Specifications (Continued)
25^oC
-40^oC TO 85^oC
-55^oC TO 125^oC
PARAMETER
Reset Pulse Width
SYMBOL V_CC (V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
t_W
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
HCT TYPES
Maximum Input Pulse
Frequency
f_MAX
4.5
25
-
20
-
16
-
MHz
Input Pulse Width
Reset Recovery Time
Reset Pulse Width
t_W
4.5
20
-
25
-
30
-
ns
t_REC
4.5
10
-
13
-
15
-
ns
t_W
4.5
20
-
25
-
30
-
ns
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
TEST
SYMBOL CONDITIONS
V_CC
(V)
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay Time
(Figure 1)
CP to Q1’ Output
t_PLH,
t_PHL
C_L = 50pF
2
-
- 140
-
175
-
210
ns
4.5
-
-
28
-
35
-
42
ns
Q_n to Q_n + 1
t_PLH,
t_PHL
C_L =15pF
C_L = 50pF
C_L = 50pF
5
-
11
-
-
-
-
-
ns
6
-
-
24
-
30
-
36
ns
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
MR to Q_n
t_PLH,
t_PHL
C_L =15pF
C_L = 50pF
C_L = 50pF
5
-
6
-
-
-
-
-
ns
6
-
-
13
-
13
-
19
ns
2
-
- 170
-
215
-
255
ns
4.5
-
-
34
-
43
-
51
ns
5
-
14
-
-
-
-
-
ns
6
-
-
29
-
27
-
43
ns
Output Transition Time
(Figure 1)
t_TLH, t_THL C_L = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
C_IN C_L = 50pF
Power Dissipation Capacitance C_PD C_L =15pF
(Notes 4, 5)
-
-
-
10
-
10
-
10
pF
5
-
30
-
-
-
-
-
pF
HCT TYPES
Propagation Delay Time
(Figure 2)
CP to Q1’ Output
Q_n to Q_n + 1
MR to Q_n
t_PLH,
t_PHL
t_PLH,
t_PHL
t_PLH,
t_PHL
C_L = 50pF
C_L =15pF
C_L = 50pF
C_L =15pF
C_L = 50pF
C_L =15pF
4.5
-
-
40
-
50
-
60
ns
5
-
17
-
-
-
-
-
ns
4.5
-
-
15
-
19
-
22
ns
5
-
6
-
-
-
-
-
ns
4.5
-
-
40
-
50
-
60
ns
5
-
17
-
-
-
-
-
ns
5