CD74HC4024 Datasheet, PDF (1/7 Pages) Texas Instruments – High Speed CMOS Logic 7-Stage Binary Ripple Counter

Data sheet acquired from Harris Semiconductor
SCHS202
November 1997
CD74HC4024,
CD74HCT4024
High Speed CMOS Logic
7-Stage Binary Ripple Counter
[ /Title
(CD74
HC402
4,
CD74
HCT40
24)
/Sub-
ject
(High
Speed
CMOS
Features
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative Edge Clocking
• TT_Ayp=ic2a5l_ofC_MAX = 60 MHz at V_CC = 5V, C_L = 15pF,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
Description
The Harris CD74HC4024 and CD74HCT4024 are 7-stage
ripple-carry binary counters. All counter stages are master-
slave flip-flops. The state of the stage advances one count
on the negative transition of each input pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
Ordering Information
PART NUMBER TEMP. RANGE (^oC) PACKAGE
PKG.
NO.
CD74HC4024E
-55 to 125
14 Ld PDIP E14.3
CD74HCT4024M
-55 to 125
14 Ld SOIC M14.15
Pinout
CD74HC4024, CD74HCT4024
(PDIP, SOIC)
TOP VIEW
CP 1
MR 2
Q₇ 3
Q₆ 4
Q₅ 5
Q₄ 6
GND 7
14 V_CC
13 NC
12 Q₁’
11 Q₂
10 NC
9 Q₃
8 NC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
1
File Number 1683.1