CD74HC4024 Datasheet, PDF (2/7 Pages) Texas Instruments – High Speed CMOS Logic 7-Stage Binary Ripple Counter

Functional Diagram
CD74HC4024, CD74HCT4024
1
CP
2
MR
12
Q₁’
11
Q₂
9
Q₃
6
Q₄
5
Q₅
4
Q₆
3
Q₇
TRUTH TABLE
CP COUNT
MR
OUTPUT STATE
↑
L
No Change
↓
L
Advance to Next State
X
H
All Outputs Are Low
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
Logic Diagram
1
CP
2
MR
7
GND
14
V_CC
CP Q
1 Q1
CP Q
R
CP Q
2
CP Q
R
CP Q
3
CP Q
R
CP Q
4
CP Q
R
CP Q
5
CP Q
R
CP Q
6
CP Q
R
CP Q
7
CP Q
R
12
Q₁’
11
Q₂
9
Q₃
6
Q₄
5
Q₅
4
Q₆
3
Q₇
2