BQ4852Y Datasheet, PDF (6/16 Pages) Texas Instruments – RTC Module With 512Kx8 NVSRAM

bq4852Y
tion byte for correction. To read the test frequency, the
bq4852Y must be selected and held in an extended read
of the seconds register, location 7FFF9, without having
the read bit set. The frequency appears on DQ0. The FTE
bit must be set using the write bit control. The FTE bit must
be reset to 0 for normal clock operation to resume.
Power-On Reset
The bq4852Y provides a power-on reset, which pulls the
RST pin low on power-down and remains low on power-
up for tCER after VCC passes VPFD.
Watchdog Timer
The watchdog circuit monitors the microprocessor’s ac-
tivity. If the processor does not reset the watchdog timer
within the programmed time-out period, the circuit as-
serts the INT or RST pin. The watchdog timer is acti-
vated by writing the desired time-out period into the
eight-bit watchdog register described in Table 3 (device
address 7FFF7). The five bits (BM4–BM0) store a bi-
nary multiplier, and the two lower-order bits
(WD1–WD0)
select
the
resolution,
where
00
=
1
16
second,
01
=
1
4
second,
10
=
1
second,
and
11
=
4
seconds.
The time-out period is the multiplication of the five-bit
multiplier with the two-bit resolution. For example,
writing 00011 in BM4–BM0 and 10 in WD1–WD0 re-
sults in a total time-out setting of 3 x 1 or 3 seconds. A
multiplier of zero disables the watchdog circuit. Bit 7 of
the watchdog register (WDS) is the watchdog steering
bit. When WDS is set to a 1 and a time-out occurs, the
watchdog asserts a reset pulse for tCER on the RST pin.
During the reset pulse, the watchdog register is cleared to all
zeros disabling the watchdog. When WDS is set to a 0, the
watchdog asserts the INT pin on a time-out. The INT pin re-
mains low until the watchdog is reset by the microprocessor
or a power failure occurs. Additionally, when the watchdog
times out, the watchdog flag bit (WDF) in the flags register,
location 7FFF0, is set.
To reset the watchdog timer, the microprocessor must
write to the watchdog register. After being reset by a
write, the watchdog time-out period starts over. As a
precaution, the watchdog circuit is disabled on a power
failure. The user must, therefore, set the watchdog at
boot-up for activation.
Interrupts
The bq4852Y allows four individually selected interrupt
events to generate an interrupt request on the INT pin.
These four interrupt events are:
n The watchdog timer interrupt, programmable to
occur according to the time-out period and conditions
described in the watchdog timer section
n The periodic interrupt, programmable to occur once
every 122µs to 500ms.
n The alarm interrupt, programmable to occur once per
second to once per month
n The power-fail interrupt, which can be enabled to be
asserted when the bq4852Y detects a power failure
The periodic, alarm, and power-fail interrupts are en-
abled by an individual interrupt-enable bit in register
7FFF6, the interrupts register. When an event occurs,
its event flag bit in the flags register, location 7FFF0, is
set. If the corresponding event enable bit is also set,
then an interrupt request is generated. Reading the
flags register clears all flag bits and makes INT high im-
pedance. To reset the flag register, the bq4852Y ad-
dresses must be held stable at location 7FFF0 for at
least 50ns to avoid inadvertent resets.
Periodic Interrupt
Bits RS3–RS0 in the interrupts register program the
rate for the periodic interrupt. The user can interpret
the interrupt in two ways: either by polling the flags
register for PF assertion or by setting PIE so that INT
goes active when the bq4852Y sets the periodic flag. Read-
ing the flags register resets the PF bit and returns INT to
the high-impedance state. Table 4 shows the periodic
rates.
Alarm Interrupt
Registers 7FFF5–7FFF2 program the real-time clock
alarm. During each update cycle, the bq4852Y com-
pares the date, hours, minutes, and seconds in the clock
registers with the corresponding alarm registers. If a
match between all the corresponding bytes is found, the
alarm flag AF in the flags register is set. If the alarm
interrupt is enabled with AIE, an interrupt request is
generated on INT. The alarm condition is cleared by a
MSB
7
WDS
6
BM4
Table 3. Watchdog Register Bits
5
BM3
Bits
4
3
BM2
BM1
2
BM0
1
WD1
LSB
0
WD0
Aug. 1996
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