BQ4852Y Datasheet, PDF (3/16 Pages) Texas Instruments – RTC Module With 512Kx8 NVSRAM

bq4852Y
Address Map
The bq4852Y provides 16 bytes of clock and control status
registers and 524,272 bytes of storage RAM.
Figure 2 illustrates the address map for the bq4852Y. Table
1 is a map of the bq4852Y registers, and Table 2 describes
the register bits.
Memory Interface
Read Mode
The bq4852Y is in read mode whenever OE (output enable)
is low and CE (chip enable) is low. The device architecture
allows ripple-through access of data from eight of 4,194,304
locations in the static storage array. Thus, the unique ad-
dress specified by the 19 address inputs defines which one
of the 524,288 bytes of data is to be accessed. Valid data is
available at the data I/O pins within tAA (address access
time) after the last address input signal is stable, providing
that the CE and OE (output enable) access times are also
satisfied. If the CE and OE access times are not met, valid
data is available after the latter of chip enable access time
(tACE) or output enable access time (tOE).
CE and OE control the state of the eight three-state data
I/O signals. If the outputs are activated before tAA, the data
lines are driven to an indeterminate state until tAA. If the
address inputs are changed while CE and OE remain low,
output data remains valid for tOH (output data hold time),
but goes indeterminate until the next address access.
Write Mode
The bq4852Y is in write mode whenever WE and CE are
active. The start of a write is referenced from the latter-
occurring falling edge of WE or CE. A write is terminated
by the earlier rising edge of WE or CE. The addresses
must be held valid throughout the cycle. CE or WE must
return high for a minimum of tWR2 from CE or tWR1 from
WE prior to the initiation of another read or write cycle.
Data-in must be valid tDW prior to the end of write and re-
main valid for tDH1 or tDH2 afterward. OE should be kept
high during write cycles to avoid bus contention; although,
if the output bus has been activated by a low on CE and
OE, a low on WE disables the outputs tWZ after WE falls.
Data-Retention Mode
With valid VCC applied, the bq4852Y operates as a
conventional static RAM. Should the supply voltage
decay, the RAM automatically power-fail deselects,
write-protecting itself tWPT after VCC falls below VPFD.
All outputs become high impedance, and all inputs are
treated as “don’t care.”
If power-fail detection occurs during a valid access, the
memory cycle continues to completion. If the memory cycle
fails to terminate within time tWPT, write-protection takes
Aug. 1996
16 Bytes
524,272
Bytes
Clock and ^7FFFF
Control Status
Registers
7FFF0
7FFEF
Storage
RAM
0000
0
Year
7FFFF
1
Month
7FFFE
2
Date
7FFFD
3
Days
7FFFC
4
Hours
7FFFB
5
Minutes 7FFFA
6
Seconds ^7FFF9
7
Control 7FFF8
8 Watchdog 7FFF7
9 Interrupts 7FFF6
10 Alarm Date 7FFF5
11 Alarm Hours 7FFF4
12 Alarm Minutes 7FFF3
13 Alarm Seconds 7FFF2
14
Tenths/
Hundredths
7FFF1
15
Flags
7FFF0
FG4852Y1
Figure 2. Address Map
3