BQ4852Y Datasheet, PDF (4/16 Pages) Texas Instruments – RTC Module With 512Kx8 NVSRAM

bq4852Y
place. When VCC drops below VSO, the control circuit
switches power to the internal energy source, which pre-
serves data.
The internal coin cell maintains data in the bq4852Y af-
ter the initial application of VCC for an accumulated period
of at least 10 years when VCC is less than VSO. As system
power returns and VCC rises above VSO, the battery is discon-
nected, and the power supply is switched to external VCC.
Write-protection continues for tCER after VCC reaches VPFD to
allow for processor stabilization. After tCER, normal RAM op-
eration can resume.
Clock Interface
Reading the Clock
The interface to the clock and control registers of the
bq4852Y is the same as that for the general-purpose
storage memory. Once every second, the user-accessible
clock/calendar locations are updated simultaneously
from the internal real time counters. To prevent reading
data in transition, updates to the bq4852Y clock regis-
ters should be halted. Updating is halted by setting the
read bit D6 of the control register to 1. As long as the
read bit is 1, updates to user-accessible clock locations
are inhibited. Once the frozen clock information is re-
trieved by reading the appropriate clock memory loca-
tions, the read bit should be reset to 0 in order to allow
updates to occur from the internal counters. Because
the internal counters are not halted by setting the read
bit, reading the clock locations has no effect on clock ac-
curacy. Once the read bit is reset to 0, within one second
the internal registers update the user-accessible regis-
ters with the correct time. A halt command issued dur-
ing a clock update allows the update to occur before
freezing the data.
Setting the Clock
Bit D7 of the control register is the write bit. Like the
read bit, the write bit when set to a 1 halts updates to
the clock/calendar memory locations. Once frozen, the
locations can be written with the desired information in
24-hour BCD format. Resetting the write bit to 0 causes
the written values to be transferred to the internal clock
counters and allows updates to the user-accessible regis-
ters to resume within one second. Use the write bit, D7,
only when updating the time registers (7FFFF–7FFF9).
Table 1. bq4842 Clock and Control Register Map
Address
7FFFF
7FFFF
7FFFD
7FFFC
7FFFB
7FFFA
7FFF9
7FFF8
7FFF7
7FFF6
7FFF5
7FFF4
7FFF3
7FFF2
7FFF1
7FFF0
D7
D6
D5
D4
10 Years
X
X
X 10 Month
X
X
10 Date
X
FTE
X
X
X
X
10 Hours
X
10 Minutes
OSC
10 Seconds
W
R
S
WDS BM4 BM3 BM2
AIE PWRIE ABE
PIE
ALM3 X
10-date alarm
ALM2 X
10-hour alarm
ALM1
Alarm 10 minutes
ALM0
Alarm 10 seconds
0.1 seconds
WDF AF PWRF BLF
D3
D2
D1
Year
Month
Date
X
Day
Hours
Minutes
Seconds
Calibration
BM1 BM0 WD1
RS3 RS2 RS1
Alarm date
Alarm hours
Alarm minutes
Alarm seconds
0.01 seconds
PF
X
X
D0
WD0
RS0
X
Notes:
X = Unused bits; can be written and read.
Clock/Calendar data in 24-hour BCD format.
BLF = 1 for low battery.
OSC = 1 stops the clock oscillator.
Interrupt enables are cleared on power-up.
Range (h)
00–99
01–12
01–31
01–07
00–23
00–59
00–59
00–31
01–31
00–23
00–59
00–59
00–99
Register
Year
Month
Date
Days
Hours
Minutes
Seconds
Control
Watchdog
Interrupts
Alarm date
Alarm hours
Alarm minutes
Alarm seconds
0.1/0.01 seconds
Flags
Aug. 1996
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