TMS320C6454BZTZ Datasheet, PDF (59/232 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6454
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SPRS311I – APRIL 2006 – REVISED MARCH 2012
3.4.2 Peripheral Configuration Register 0 Description
The Peripheral Configuration Register (PERCFG0) is used to change the state of the peripherals. One
write is allowed to this register within 16 SYSCLK3 cycles after the correct key is written to the PERLOCK
register.
NOTE
The instructions that write to the PERLOCK and PERCFG0 registers must be in the same
fetch packet if code is being executed from external memory. If the instructions are in
different fetch packets, fetching the second instruction from external memory may stall the
instruction long enough that the PERCFG0 register is locked before the instruction is
executed.
31
24
Reserved
R/W-0
23
21
Reserved
R/W-0
20
PCICTL
R/W-0
19
Reserved
R/W-0
18
HPICTL
R/W-0
17
Reserved
R/W-0
16
McBSP1CTL
R/W-0
15
Reserved
R/W-0
14
McBSP0CTL
R/W-0
13
Reserved
R/W-0
12
I2CCTL
R/W-0
11
Reserved
R/W-0
10
GPIOCTL
R/W-0
9
Reserved
R/W-0
8
TIMER1CTL
R/W-0
7
6
5
4
3
0
Reserved
TIMER0CTL
Reserved
EMACCTL
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 3-4. Peripheral Configuration Register 0 (PERCFG0) - 0x02AC 0008
Table 3-7. Peripheral Configuration Register 0 (PERCFG0) Field Descriptions
Bit
31:21
20
Field
Reserved
PCICTL
19 Reserved
18 HPICTL
17 Reserved
16 McBSP1CTL
15 Reserved
14 McBSP0CTL
13 Reserved
Value
0
1
0
1
1
0
1
0
1
Description
Reserved.
Mode control for PCI. This bit defaults to 1 when host boot is used (BOOTMODE[3:0] = 0111b).
Set PCI to disabled mode
Set PCI to enabled mode
Reserved.
Mode control for HPI. This bit defaults to 1 when host boot is used (BOOTMODE[3:0] = 0001b).
Set HPI to disabled mode
Set HPI to enabled mode
Reserved.
Mode control for McBSP1
Set McBSP1 to disabled mode
Set McBSP1 to enabled mode
Reserved.
Mode control for McBSP0
Set McBSP0 to disabled mode
Set McBSP0 to enabled mode
Reserved.
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