TMS320C6454BZTZ Datasheet, PDF (222/232 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6454
SPRS311I – APRIL 2006 – REVISED MARCH 2012
www.ti.com
7.17 General-Purpose Input/Output (GPIO)
7.17.1 GPIO Device-Specific Information
On the C6454 device, the GPIO peripheral pins GP[15:8] and GP[3:0] are muxed with the PCI and
McBSP1 peripheral pins and the SYSCLK4 signal. For more detailed information on device/peripheral
configuration and the C6454 device pin muxing, see Section 3, Device Configuration.
7.17.2 GPIO Peripheral Register Descriptions
HEX ADDRESS RANGE
02B0 0008
02B0 000C
02B0 0010
02B0 0014
02B0 0018
02B0 001C
02B0 0020
02B0 0024
02B0 0028
02B0 002C
02B0 0030
02B0 008C
02B0 0090 - 02B0 00FF
02B0 0100 - 02B0 3FFF
Table 7-102. GPIO Registers
ACRONYM
BINTEN
-
DIR
OUT_DATA
SET_DATA
CLR_DATA
IN_DATA
SET_RIS_TRIG
CLR_RIS_TRIG
SET_FAL_TRIG
CLR_FAL_TRIG
-
-
-
REGISTER NAME
GPIO interrupt per bank enable register
Reserved
GPIO Direction Register
GPIO Output Data register
GPIO Set Data register
GPIO Clear Data Register
GPIO Input Data Register
GPIO Set Rising Edge Interrupt Register
GPIO Clear Rising Edge Interrupt Register
GPIO Set Falling Edge Interrupt Register
GPIO Clear Falling Edge Interrupt Register
Reserved
Reserved
Reserved
222 C64x+ Peripheral Information and Electrical Specifications
Copyright © 2006–2012, Texas Instruments Incorporated
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