TMS320C6454BZTZ Datasheet, PDF (138/232 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6454
SPRS311I – APRIL 2006 – REVISED MARCH 2012
www.ti.com
7.7.3.7 PLL Controller Status Register
The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in
Figure 7-17 and described in Table 7-25.
31
Reserved
R-0
15
1
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-17. PLL Controller Status Register (PLLSTAT) [Hex Address: 029A 013C]
16
0
GOSTAT
R-0
Bit Field
31:1 Reserved
0 GOSTAT
Table 7-25. PLL Controller Status Register (PLLSTAT) Field Descriptions
Value
0
0
1
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
GO operation status.
GO operation is not in progress. SYSCLK divide ratios are not being changed.
GO operation is in progress. SYSCLK divide ratios are being changed.
138 C64x+ Peripheral Information and Electrical Specifications
Copyright © 2006–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320C6454