TMS320C6454BZTZ Datasheet, PDF (161/232 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6454
SPRS311I – APRIL 2006 – REVISED MARCH 2012
AECLKOUT
READ latency = 2
ACEx
ABE[7:0]
AEA[19:0]/ABA[1:0]
AED[63:0]
ASADS/ASRE^(B)
1
2
BE1
4
EA1
8
1
BE2
BE3
EA2
EA3
6
Q1
BE4
EA4
7
Q2
3
5
Q3
Q4
8
9
9
AAOE/ASOE^(B)
AAWE/ASWE^(B)
A The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):
−Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency
−Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency
−ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been
issued (CE_EXT = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (CE_EXT = 1).
−Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect
cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (R_ENABLE = 1).
−In this figure R_LTNCY = 2, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.
B AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.
Figure 7-36. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2)^(A)
AECLKOUT
ACEx
ABE[7:0]
AEA[19:0]/ABA[1:0]
AED[63:0]
ASADS/ASRE^(B)
1
1
2
3
BE1
BE2
BE3
BE4
4
5
EA1
EA2
EA3
EA4
10
10
11
Q1
Q2
Q3
Q4
8
8
AAOE/ASOE^(B)
12
12
AAWE/ASWE^(B)
A The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):
− Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency
− Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency
− ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been
issued (CE_EXT = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (CE_EXT = 1).
− Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect
cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (R_ENABLE = 1).
− In this figure W_LTNCY = 0, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.
B AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.
Figure 7-37. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)^(A)
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C64x+ Peripheral Information and Electrical Specifications 161
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