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MSP430F543X_1 Datasheet, PDF (58/90 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
AVCC
V(Ax)
IADC12_A
IREF+
CI
RI
PARAMETER
Analog supply voltage
Analog input voltage range(2)
Operating supply current into
AVCC terminal(3)
Operating supply current into
AVCC terminal(4)
Input capacitance
Input MUX ON resistance
TEST CONDITIONS
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
All ADC12 pins: P6.0 to P6.7, P7.4 to P7.7,
P5.0, and P5.1 terminals
fADC12CLK = 5.0 MHz, ADC12ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC12DIV = 0
ADC12ON = 0,
REFON = 1, REF2_5V = 1
ADC12ON = 0,
REFON = 1, REF2_5V = 0
Only one terminal Ax can be selected at one
time
0 V ≤ VAx ≤ AVCC
VCC
2.2 V
3V
3V
2.2 V/3 V
2.2 V
MIN TYP MAX UNIT
2.2
3.6 V
0
AVCC V
125 155
µA
150 220
150 190
µA
150 180
20
25 pF
10 200 1900 Ω
(1) The leakage current is specified by the digital I/O input leakage.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
(3) The internal reference supply current is not included in current consumption parameter IADC12.
(4) The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion. No external load.
12-Bit ADC, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
VeREF+
VREF–/VeREF–
(VeREF+ –
VREF–/VeREF–)
IVeREF+
IVREF–/VeREF–
PARAMETER
Positive external reference voltage input
Negative external reference voltage input
Differential external reference voltage
input
Static input current
Static input current
TEST CONDITIONS
VeREF+ > VREF–/VeREF– (2)
VeREF+ > VREF–/VeREF– (3)
VeREF+ > VREF–/VeREF– (4)
0 V ≤ VeREF+ ≤ VAVCC
0 V ≤ VeREF– ≤ VAVCC
VCC
2.2 V/3 V
2.2 V/3 V
MIN TYP MAX UNIT
1.4
AVCC V
0
1.2 V
1.4
AVCC V
±1 µA
±1 µA
(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
12-Bit ADC, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VREF+
Positive built-in reference
voltage output
AVCC(min)
IVREF+
AVCC minimum voltage,
Positive built-in reference
active
Load current out of VREF+
terminal
TEST CONDITIONS
REF2_5V = 1 for 2.5 V,
IVREF+(max) ≤ IVREF+ ≤ IVREF+(min)
REF2_5V = 0 for 1.5 V,
IVREF+(max) ≤ IVREF+ ≤ IVREF+(min)
REF2_5V = 0
REF2_5V = 1
VCC
3V
2.2 V/3 V
2.2 V
3V
MIN TYP
2.35 2.45
1.41 1.47
2.2
2.8
MAX UNIT
2.53
V
1.53
V
–1
mA
–1
58
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