MSP430F543X_1 Datasheet, PDF(13/90 Page) Texas Instruments

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MSP430F543X_1 Datasheet, PDF (13/90 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430F543x, MSP430F541x

MSP430F543xA, MSP430F541xA

www.ti.com.......................................................................................................................................................................................... SLAS612 â SEPTEMBER 2008

Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE

System Reset

Power-Up

External Reset

Watchdog Timeout, Key Violation

Flash Memory Key Violation

System NMI

PMM

Vacant Memory Access

JTAG Mailbox

User NMI

NMI

Oscillator Fault

Flash Memory Access Violation

Timer_B7

Watchdog Timer_A Interval Timer

Mode

USCI_A0 Receive/Transmit

USCI_B0 Receive/Transmit

ADC12_A

Timer0_A5

USCI_A2 Receive/Transmit

USCI_B2 Receive/Transmit

DMA

Timer1_A3

I/O Port P1

USCI_A1 Receive/Transmit

USCI_B1 Receive/Transmit

USCI_A3 Receive/Transmit

USCI_B3 Receive/Transmit

I/O Port P2

RTC_A

INTERRUPT FLAG

WDTIFG, KEYV (SYSRSTIV)(1)(2)

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,

JMBOUTIFG (SYSSNIV)(1)

NMIIFG, OFIFG, ACCVIFG (SYSUNIV)(1)(2)

TBCCR0 CCIFG0 (3)

TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,

TBIFG (TBIV)(1)(3)

WDTIFG

UCA0RXIFG, UCA0TXIFG (UCA0IV)(1)(3)

UCB0RXIFG, UCB0TXIFG (UCAB0IV)(1)(3)

ADC12IFG0 ... ADC12IFG15 (ADC12IV)(1)(3)

TA0CCR0 CCIFG0(3)

TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,

TA0IFG (TA0IV)(1)(3)

UCA2RXIFG, UCA2TXIFG (UCA2IV)(1)(3)

UCB2RXIFG, UCB2TXIFG (UCB2IV)(1)(3)

DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1)(3)

TA1CCR0 CCIFG0(3)

TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,

TA1IFG (TA1IV)(1)(3)

P1IFG.0 to P1IFG.7 (P1IV)(1)(3)

UCA1RXIFG, UCA1TXIFG (UCA1IV)(1)(3)

UCB1RXIFG, UCB1TXIFG (UCB1IV)(1)(3)

UCA3RXIFG, UCA3TXIFG (UCA3IV)(1)(3)

UCB3RXIFG, UCB3TXIFG (UCB3IV)(1)(3)

P2IFG.0 to P2IFG.7 (P2IV)(1)(3)

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RT0PSIFG, RT1PSIFG (RTCIV)(1)(3)

Reserved

Reserved (4)

SYSTEM

INTERRUPT

WORD

ADDRESS

PRIORITY

Reset

0FFFEh

63, highest

(Non)maskable

0FFFCh

(Non)maskable

Maskable

0FFFAh

0FFF8h

0FFF6h

0FFF4h

0FFF2h

0FFF0h

0FFEEh

0FFECh

0FFEAh

0FFE8h

0FFE6h

0FFE4h

0FFE2h

0FFE0h

0FFDEh

0FFDCh

0FFDAh

0FFD8h

0FFD6h

0FFD4h

0FFD2h

0FFD0h

â®

0FF80h

â®

0, lowest

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(3) Interrupt flags are located in the module.

(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatibility with other devices, it is recommended to reserve these locations.

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