ADS62P25 Datasheet, PDF (58/71 Pages) Texas Instruments – DUAL CHANNEL, 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS62P25, ADS62P24
ADS62P23, ADS62P22
SLAS576A – OCTOBER 2007 – REVISED FEBRUARY 2008
COEFFICIENTS
h0
h1
h2
h3
h4
h5
h6
h7
h8
h9
h10
h11
Table 23. Predefined Coefficients for Decimation by 2 Filters
LOW-PASS FILTER
23
-37
-6
68
-36
-61
35
118
-100
-197
273
943
DECIMATE BY 2
HIGH-PASS FILTER
-22
-65
-52
30
66
-35
-107
38
202
-41
-644
1061
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COEFFICIENTS
h0
h1
h2
h3
h4
h5
h6
h7
h8
h9
h10
h11
Table 24. Predefined Coefficients for Decimation by 4 Filters
LOW-PASS FILTER
-17
-50
71
46
24
-42
-100
-97
8
202
414
554
DECIMATE BY 4
1st BAND-PASS FILTER
2ND BAND-PASS FILTER
-7
-34
19
-34
-47
-101
127
43
73
58
0
-28
86
-5
117
-179
-190
294
-464
86
-113
-563
526
352
HIGH-PASS FILTER
32
-15
-95
22
-8
-81
106
-62
-97
310
-501
575
Custom Filter Coefficients with Decimation
The filter coefficients can also be programmed by the user (custom). For custom coefficients, set the register bit
(FILTER COEFF SELECT) and load the coefficients (h0 to h11) in registers 1E to 2F using the serial interface
(Table 25) as:
Register content = 12 bit signed representation of [real coefficient value × 2¹¹]
58
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