ADS62P25 Datasheet, PDF (45/71 Pages) Texas Instruments – DUAL CHANNEL, 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

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ADS62P25, ADS62P24
ADS62P23, ADS62P22
SLAS576A – OCTOBER 2007 – REVISED FEBRUARY 2008
In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally.
COARSE GAIN AND PROGRAMMABLE FINE GAIN
ADS62P2X includes gain settings that can be used to get improved SFDR performance (over 0 dB gain mode).
For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 18.
The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The
fine gain is programmable in 0.5 dB steps from 0 to 6 dB; however the SFDR improvement is achieved at the
expense of SNR. So, the programmable fine gain makes it possible to trade-off between SFDR and SNR. The
coarse gain makes it possible to get best SFDR but without losing SNR significantly.
The gains can be programmed using the serial interface (bits COARSE GAIN and FINE GAIN). Note that the
default gain after reset is 0 dB.
Table 18. Full-Scale Range Across Gains
GAIN, dB
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
TYPE
Default after reset
Coarse (fixed)
Fine (programmable)
FULL-SCALE, V_PP
2V
1.34
1.89
1.78
1.68
1.59
1.50
1.42
1.34
1.26
1.19
1.12
1.06
1.00
CLOCK INPUT
The clock inputs can be driven differentially (sine, LVPECL or LVDS) or single-ended (LVCMOS), with little or no
difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using
internal 5 kΩ resistors as shown in Figure 88. This allows using transformer-coupled drive circuits for sine wave
clock or ac-coupling for LVPECL, LVDS clock sources (Figure 90 and Figure 91).
Copyright © 2007–2008, Texas Instruments Incorporated
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Product Folder Link(s): ADS62P25, ADS62P24 ADS62P23, ADS62P22