ADS62P25 Datasheet, PDF (1/71 Pages) Texas Instruments – DUAL CHANNEL, 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

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ADS62P25, ADS62P24
ADS62P23, ADS62P22
SLAS576A – OCTOBER 2007 – REVISED FEBRUARY 2008
DUAL CHANNEL, 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
FEATURES
1
• Maximum Sample Rate: 125 MSPS
• 12-Bit Resolution with No Missing Codes
• 95 dB Crosstalk
• Parallel CMOS and DDR LVDS Output Options
• 3.5 dB Coarse Gain and Programmable Fine
Gain up to 6 dB for SNR/SFDR Trade-Off
• Digital Processing Block with:
– Offset Correction
– Fine Gain Correction, in Steps of 0.05 dB
– Decimation by 2/4/8
– Built-in and Custom Programmable 24-Tap
Low-/High-/Band-Pass Filters
• Supports Sine, LVPECL, LVDS, and LVCMOS
Clocks and Amplitude Down to 400 mV_PP
• Clock Duty Cycle Stabilizer
• Internal Reference; Supports External
Reference also
• 64-QFN Package (9mm × 9mm)
• Pin Compatible 14-Bit Family (ADS62P4X)
APPLICATIONS
• Wireless Communications Infrastructure
• Software Defined Radio
• Power Amplifier Linearization
• 802.16d/e
• Test and Measurement Instrumentation
• High Definition Video
• Medical Imaging
• Radar Systems
DESCRIPTION
ADS62P2X is a dual channel 12-bit A/D converter
family with maximum sample rates up to 125 MSPS.
It combines high performance and low power
consumption in a compact 64 QFN package. Using
an internal sample and hold and low jitter clock
buffer, the ADC supports high SNR and high SFDR at
high input frequencies. It has coarse and fine gain
options that can be used to improve SFDR
performance at lower full-scale input ranges.
ADS62P2X includes a digital processing block that
consists of several useful and commonly used digital
functions such as ADC offset correction, fine gain
correction (in steps of 0.05 dB), decimation by 2,4,8
and in-built and custom programmable filters. By
default, the digital processing block is bypassed, and
its functions are disabled.
Two output interface options exist – parallel CMOS
and DDR LVDS (Double Data Rate). ADS62P2X
includes internal references while traditional
reference pins and associated decoupling capacitors
have been eliminated. Nevertheless, the device can
also be driven with an external reference. The device
is specified over the industrial temperature range
(–40°C to 85°C).
ADS62P2X Performance Summary
SFDR, dBc ^{Fin = 10 MHz (0 dB gain)}
F_in = 190 MHz (3.5 dB gain)
SINAD, dBFS ^{Fin = 10 MHz (0 dB gain)}
F_in = 190 MHz (3.5 dB gain)
Analog power, mW
ADS62P25
88
84
71
69.5
799
ADS62P24
92
86
71.3
69.5
710
ADS62P23
93
87
71.5
69.7
594
ADS62P22
94
85
71.5
69.2
515
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated