TMS320VC5505_10 Datasheet, PDF (56/135 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5505
SPRS503B – JUNE 2009 – REVISED JANUARY 2010
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Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature
(Unless Otherwise Noted) (continued)
PARAMETER
TEST CONDITIONS ⁽¹⁾
MIN
TYP
MAX UNIT
All Pins (except USB, EMIF, CLKOUT, and
GPAIN[3:0] pins)
+4 mA
I_OL
Low-level output current [DC]
EMIF pins
CLKOUT pin
GPAIN[3:0]
DV_DD = 3.3 V
DV_DD = 1.8 V
DV_DD = 3.3 V
DV_DD = 1.8 V
DV_DD = V_{DDA_ANA} = 1.3 V,
external regulator
DV_DD = V_{DDA_ANA} = 1.3 V,
internal regulator⁽⁸⁾
+6 mA
+5 mA
+6 mA
+4 mA
+4 mA
+4 mA
I_OZ ⁽⁹⁾ I/O Off-state output current
All Pins (except USB and GPAIN[3:0])
GPAIN[3:0] pins
-10
+10 mA
-10
+10 mA
Active, CV_DD = 1.3 V, DSP clock = 100 MHz
Room Temp (25 °C), 75% DMAC + 25% ADD
(typical sine wave data switching)
0.22
mW/MHz
Active, CV_DD = 1.05 V, DSP clock = 60 MHz
Room Temp (25 °C), 75% DMAC + 25% ADD
(typical data switching)
0.15
mW/MHz
Active, CV_DD = 1.3 V, DSP clock = 100 MHz
Room Temp (25 °C), 75% DMAC + 25% NOP
(typical sine wave data switching)
0.22
mW/MHz
Active, CV_DD = 1.05 V, DSP clock = 60 MHz
Room Temp (25 °C), 75% DMAC + 25% NOP
(typical data switching)
0.14
mW/MHz
Active, CV_DD = 1.3 V, DSP clock = 100 MHz
Room Temp (25 °C), Hardware FFT Accelerator
1024-pt FFT, ROM execution
0.31
mW/MHz
Core (CV_DD) supply current
I_CDD
Active, CV_DD = 1.05 V, DSP clock = 60 MHz
Room Temp (25 °C), Hardware FFT Accelerator
1024-pt FFT, ROM execution
Standby, CV_DD = 1.3 V, Master clock disabled,
Room Temp (25 °C), DARAM and SARAM in active
mode
Standby, CV_DD = 1.05 V, Master clock disabled,
Room Temp (25 °C), DARAM and SARAM in active
mode
0.25
mW/MHz
0.44
mW
0.26
mW
Standby, CV_DD = 1.3 V, Master clock disabled,
Room Temp (25 °C), DARAM in retention and
SARAM in active mode
0.40
mW
Standby, CV_DD = 1.05 V, Master clock disabled,
Room Temp (25 °C), DARAM in retention and
SARAM in active mode
0.23
mW
Standby, CV_DD = 1.3 V, Master clock disabled,
Room Temp (25 °C), DARAM in active mode and
SARAM in retention
0.28
mW
Standby, CV_DD = 1.05 V, Master clock disabled,
Room Temp (25 °C), DARAM in active mode and
SARAM in retention
0.15
mW
Analog PLL (V_{DDA_PLL}) supply
current
V_{DDA_PLL} = 1.37 V
Room Temp (25 °C), Phase detector = 170 kHz,
VCO = 120 MHz
0.7
1.2 mA
SAR Analog (V_{DDA_ANA}) supply
current
V_{DDA_ANA} = 1.37 V, SAR clock = 2 MHz, Temp (70
°C)
1 mA
C_I
Input capacitance
C_o
Output capacitance
4 pF
4 pF
(9) I_OZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
56
Device Operating Conditions
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