TMS320VC5505_10 Datasheet, PDF (121/135 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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CPU WORD
ADDRESS
A000h
A001h
A800h + 4 × N
A801h + 4 × N
C000h
C001h
C008h
C009h
C020h
C021h
C024h
C025h
C028h
C029h
C02Ch
C02Dh
C080h
C081h
C084h
C085h
C088h
C089h
C090h
C091h
C094h
C095h
C098h
C099h
D000h + 16 × R
D001h + 16 × R
D004h + 16 × R
D005h + 16 × R
E000h + 16 × N
E001h + 16 × N
E004h + 16 × N
E005h + 16 × N
E008h + 16 × N
E009h + 16 × N
E00Ch + 16 × N
E00Dh + 16 × N
E800h + 16 × N
E801h + 16 × N
E804h + 16 × N
E805h + 16 × N
E808h + 16 × N
TMS320VC5505
SPRS503B – JUNE 2009 – REVISED JANUARY 2010
Table 6-43. Universal Serial Bus (USB) Registers ⁽¹⁾ (continued)
ACRONYM
REGISTER DESCRIPTION
DMA_SCHED_CTRL1
DMA_SCHED_CTRL2
ENTRYLSW[N]
ENTRYMSW[N]
-
-
DIVERSION1
DIVERSION2
FDBSC0
FDBSC1
FDBSC2
FDBSC3
FDBSC4
FDBSC5
FDBSC6
FDBSC7
LRAM0BASE1
LRAM0BASE2
LRAM0SIZE
-
LRAM1BASE1
LRAM1BASE2
PEND0
PEND1
PEND2
PEND3
PEND4
PEND5
QMEMRBASE1[R]
QMEMRBASE2[R]
QMEMRCTRL1[R]
QMEMRCTRL2[R]
CTRL1A
CTRL2A
CTRL1B
CTRL2B
CTRL1C
CTRL2C
CTRL1D
CTRL2D
QSTAT1A
QSTAT2A
QSTAT1B
QSTAT2B
QSTAT1C
CDMA Scheduler Control Register 1
CDMA Scheduler Control Register 1
CDMA Scheduler Table Word N Registers LSW (N = 0 to 63)
CDMA Scheduler Table Word N Registers MSW (N = 0 to 63)
Queue Manager (QMGR) Registers
Reserved
Reserved
Queue Manager Queue Diversion Register 1
Queue Manager Queue Diversion Register 2
Queue Manager Free Descriptor/Buffer Starvation Count Register 0
Queue Manager Free Descriptor/Buffer Starvation Count Register 1
Queue Manager Free Descriptor/Buffer Starvation Count Register 2
Queue Manager Free Descriptor/Buffer Starvation Count Register 3
Queue Manager Free Descriptor/Buffer Starvation Count Register 4
Queue Manager Free Descriptor/Buffer Starvation Count Register 5
Queue Manager Free Descriptor/Buffer Starvation Count Register 6
Queue Manager Free Descriptor/Buffer Starvation Count Register 7
Queue Manager Linking RAM Region 0 Base Address Register 1
Queue Manager Linking RAM Region 0 Base Address Register 2
Queue Manager Linking RAM Region 0 Size Register
Reserved
Queue Manager Linking RAM Region 1 Base Address Register 1
Queue Manager Linking RAM Region 1 Base Address Register 2
Queue Manager Queue Pending 0
Queue Manager Queue Pending 1
Queue Manager Queue Pending 2
Queue Manager Queue Pending 3
Queue Manager Queue Pending 4
Queue Manager Queue Pending 5
Queue Manager Memory Region R Base Address Register 1 (R = 0 to 15)
Queue Manager Memory Region R Base Address Register 2 (R = 0 to 15)
Queue Manager Memory Region R Control Register (R = 0 to 15)
Queue Manager Memory Region R Control Register (R = 0 to 15)
Queue Manager Queue N Control Register 1A (N = 0 to 63)
Queue Manager Queue N Control Register 2A (N = 0 to 63)
Queue Manager Queue N Control Register 1B (N = 0 to 63)
Queue Manager Queue N Control Register 2B (N = 0 to 63)
Queue Manager Queue N Control Register 1C (N = 0 to 63)
Queue Manager Queue N Control Register 2C (N = 0 to 63)
Queue Manager Queue N Control Register 1D (N = 0 to 63)
Queue Manager Queue N Control Register 2D (N = 0 to 63)
Queue Manager Queue N Status Register 1A (N = 0 to 63)
Queue Manager Queue N Status Register 2A (N = 0 to 63)
Queue Manager Queue N Status Register 1B (N = 0 to 63)
Queue Manager Queue N Status Register 2B (N = 0 to 63)
Queue Manager Queue N Status Register 1C (N = 0 to 63)
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Peripheral Information and Electrical Specifications 121
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