TM4C123GH6PZI Datasheet, PDF (559/1435 Pages) Texas Instruments – Tiva TM4C123GH6PZ Microcontroller

Tiva^™ TM4C123GH6PZ Microcontroller _{(identical to LM4F232H5QC)}
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PROGMISC reserved ERMISC INVDMISC VOLTMISC
reserved
EMISC PMISC AMISC
Type RO
RO R/W1C RO R/W1C R/W1C R/W1C RO
RO
RO
RO
RO
RO R/W1C R/W1C R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:14
13
Name
reserved
PROGMISC
Type
RO
R/W1C
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PROGVER Masked Interrupt Status and Clear
Value Description
0 When read, a 0 indicates that an interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
1 When read, a 1 indicates that an unmasked interrupt was
signaled.
Writing a 1 to this bit clears PROGMISC and also the PROGRIS
bit in the FCRIS register (see page 554).
12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
ERMISC
R/W1C
0
ERVER Masked Interrupt Status and Clear
Value Description
0 When read, a 0 indicates that an interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
1 When read, a 1 indicates that an unmasked interrupt was
signaled.
Writing a 1 to this bit clears ERMISC and also the ERRIS bit in
the FCRIS register (see page 554).
July 17, 2013
559
Texas Instruments-Production Data