TM4C123GH6PZI Datasheet, PDF (1033/1435 Pages) Texas Instruments – Tiva TM4C123GH6PZ Microcontroller

Tiva^™ TM4C123GH6PZ Microcontroller _{(identical to LM4F232H5QC)}
Write the I2CMTPR register with the value of 0x0000.0003.
8. To send the master code byte, software should place the value of the master code byte into the
I2CMSA register and write the I2CMCS register with a value of 0x13.
9. This places the I2C master peripheral in High-speed mode, and all subsequent transfers (until
STOP) are carried out at High-speed data rate using the normal I2CMCS command bits, without
setting the HS bit in the I2CMCS register.
10. The transaction is ended by setting the STOP bit in the I2CMCS register.
11. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
12. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged.
16.5
Register Map
Table 16-4 on page 1033 lists the I²C registers. All addresses given are relative to the I²C base address:
■ I²C 0: 0x4002.0000
■ I²C 1: 0x4002.1000
■ I²C 2: 0x4002.2000
■ I²C 3: 0x4002.3000
■ I²C 4: 0x400C.0000
■ I²C 5: 0x400C.1000
Note that the I²C module clock must be enabled before the registers can be programmed (see
page 349). There must be a delay of 3 system clocks after the I²C module clock is enabled before
any I²C module registers are accessed.
The hw_i2c.h file in the TivaWare^™ Driver Library uses a base address of 0x800 for the I²C slave
registers. Be aware when using registers with offsets between 0x800 and 0x818 that TivaWare™
for C Series uses an offset between 0x000 and 0x018 with the slave base address.
Table 16-4. Inter-Integrated Circuit (I²C) Interface Register Map
Offset Name
I²C Master
0x000 I2CMSA
0x004 I2CMCS
0x008 I2CMDR
0x00C I2CMTPR
0x010 I2CMIMR
0x014 I2CMRIS
0x018 I2CMMIS
0x01C I2CMICR
0x020 I2CMCR
Type
Reset
Description
R/W
0x0000.0000 I2C Master Slave Address
R/W
0x0000.0020 I2C Master Control/Status
R/W
0x0000.0000 I2C Master Data
R/W
0x0000.0001 I2C Master Timer Period
R/W
0x0000.0000 I2C Master Interrupt Mask
RO
0x0000.0000 I2C Master Raw Interrupt Status
RO
0x0000.0000 I2C Master Masked Interrupt Status
WO
0x0000.0000 I2C Master Interrupt Clear
R/W
0x0000.0000 I2C Master Configuration
See
page
1035
1036
1041
1042
1043
1044
1045
1046
1047
July 17, 2013
Texas Instruments-Production Data
1033