TM4C123GH6PZI Datasheet, PDF (454/1435 Pages) Texas Instruments – Tiva TM4C123GH6PZ Microcontroller

System Control
Register 132: Software Reset Control 1 (SRCR1), offset 0x044
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 2 (DC2) register.
Important: This register is provided for legacy software support only.
The peripheral-specific Software Reset registers (such as SRTIMER) should be used
to reset specific peripherals. A write to this register also writes the corresponding bit in
the peripheral-specific register. Any bits that are changed by writing to this register can
be read back correctly with a read of this register. Software must use the
peripheral-specific registers to support modules that are not present in the legacy
registers. If software uses a peripheral-specific register to write a legacy peripheral
(such as TIMER0), the write causes proper operation, but the value of that bit is not
reflected in this register. If software uses both legacy and peripheral-specific register
accesses, the peripheral-specific registers must be accessed by read-modify-write
operations that affect only peripherals that are not present in the legacy registers. In
this manner, both the peripheral-specific and legacy registers have coherent information.
Note that the Software Reset Analog Comparator (SRACMP) register has only one
bit to set the analog comparator module. Resetting the module resets all the blocks. If
any of the COMPn bits are set, the entire analog comparator module is reset. It is not
possible to reset the blocks individually.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type RO, reset 0x0000.0000
31
30
29
28
27
reserved
Type RO
RO
RO
RO
RO
Reset
0
0
0
0
0
26
25
24
COMP2 COMP1 COMP0
RO
RO
RO
0
0
0
15
reserved
Type RO
Reset
0
14
I2C1
RO
0
13
reserved
RO
0
12
I2C0
RO
0
11
10
reserved
RO
RO
0
0
9
QEI1
RO
0
8
QEI0
RO
0
23
22
21
reserved
RO
RO
RO
0
0
0
7
6
reserved
RO
RO
0
0
5
SSI1
RO
0
20
19
18
17
16
TIMER3 TIMER2 TIMER1 TIMER0
RO
RO
RO
RO
RO
0
0
0
0
0
4
SSI0
RO
0
3
2
1
0
reserved UART2 UART1 UART0
RO
RO
RO
RO
0
0
0
0
Bit/Field
31:27
26
25
Name
reserved
COMP2
COMP1
Type
RO
RO
RO
Reset
0
0x0
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Analog Comp 2 Reset Control
When this bit is set, Analog Comparator module 2 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
Analog Comp 1 Reset Control
When this bit is set, Analog Comparator module 1 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
454
July 17, 2013
Texas Instruments-Production Data