TMS320DM647_08 Datasheet, PDF (55/167 Pages) Texas Instruments – Digital Media Processor

www.ti.com
6 Peripheral Information and Electrical Specifications
6.1 Parameter Information
Tester Pin Electronics
42 Ω
4.0 pF
3.5 nH
1.85 pF
Transmission Line
Z0 = 50 Ω
(see Note)
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372A – MAY 2007 – REVISED JUNE 2007
Data Sheet Timing Reference Point
Output
Under
Test
Device Pin
(see Note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must
be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission
line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 6-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of ac timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1.1 3.3-V Signal Transition Levels
All input and output timing parameters are referenced to V_ref for both 0 and 1 logic levels. For 3.3-V I/O,
V_ref = 1.5 V. For 1.8-V I/O, V_ref = 0.9 V.
Vref
Figure 6-2. Input and Output Voltage Reference Levels for ac Timing Measurements
All rise and fall transition timing parameters are referenced to V_IL MAX and V_IH MIN for input clocks,
V_OLMAX and V_OH MIN for output clocks.
V_ref = V_IH MIN (or V_OH MIN)
V_ref = V_IL MAX (or V_OL MAX)
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels
6.1.2 3.3-V Signal Transition Rates
All timings are tested with an input edge rate of 4 volts per nanosecond (4 Vpns).
Submit Documentation Feedback
Peripheral Information and Electrical Specifications
55