TMS320DM647_08 Datasheet, PDF (1/167 Pages) Texas Instruments – Digital Media Processor

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1 TMS320DM647/TMS320DM648 Digital Media Processor
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372A – MAY 2007 – REVISED JUNE 2007
1.1 Features
• High-Performance Digital Media Processor
(DM647/DM648)
– 720, 900-MHz C64x+™ Clock Rate
– 1.39, 1.11-ns Instruction Cycle Time
– 5760, 7200 MIPS
– Eight 32-Bit C64x+ Instructions/Cycle
– Fully Software-Compatible With
C64x/Debug
– Commercial Temperature Ranges
• VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
– Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
• Six ALUs (32-/40-Bit), Each Supports
Single 32-bit, Dual 16-bit, or Quad 8-bit
Arithmetic per Clock Cycle
• Two Multipliers Support Four 16 x 16-bit
Multiplies (32-bit Results) per Clock
Cycle or Eight 8 x 8-bit Multiplies (16-Bit
Results) per Clock Cycle
– Load-Store Architecture With Non-Aligned
Support
– 64 32-bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Additional C64x+™ Enhancements
• Protected Mode Operation
• Exceptions Support for Error Detection
and Program Redirection
• Hardware Support for Modulo Loop
Auto-Focus Module Operation
• C64x+ Instruction Set Features
– Byte-Addressable (8-/16-/32-/64-bit Data)
– 8-bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– VelociTI.2 Increased Orthogonality
– C64x+ Extensions
• Compact 16-bit Instructions
• Additional Instructions to Support
Complex Multiplies
• C64x+ L1/L2 Memory Architecture
– 256K-bit (32K-byte) L1P Program Cache
[Direct Mapped]
– 256K-bit (32K-byte) L1D Data Cache
[2-Way Set-Associative]
– 2M-bit/256K-byte (DM647) or
4M-Bit/512K-byte) (DM648) L2 Unified
Mapped RAM/Cache [Flexible Allocation]
• Supports Little Endian Mode Only
• Five Configurable Video Ports
– Providing a Glueless I/F to Common Video
Decoder and Encoder Devices
– Supports Multiple Resolutions/Video Stds
• VCXO Interpolated Control Port (VIC)
– Supports Audio/Video Synchronization
• External Memory Interfaces (EMIFs)
– 32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
– Asynchronous 16-Bit Wide EMIF (EMIFA)
With up to 64M-Byte Address Reach
– Glueless Interface to Asynchronous
Memories (SRAM, Flash, and EEPROM)
– Synchronous Memories (SBSRAM and ZBT
SRAM)
– Supports Interface to Standard Sync
Devices and Custom Logic (FPGA, CPLD,
ASICs, etc)
• Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
• 3-Port Gigabit Ethernet Switch Subsystem
• Four 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
• One UART (With RTS and CTS Flow Control)
• One 4-wire Serial Port Interface (SPI) With Two
Chip-Selects
• Master/Slave Inter-Integrated Circuit (I2C
Bus™)
• Multichannel Audio Serial Port (McASP)
– Ten Serializers and SPDIF (DIT) Mode
• 16/32-Bit Host-Port Interface (HPI)
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.3
• VLYNQ™ Interface (FPGA Interface)
• On-Chip ROM Bootloader
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