TMS320DM647_08 Datasheet, PDF (108/167 Pages) Texas Instruments – Digital Media Processor

TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372A – MAY 2007 – REVISED JUNE 2007
www.ti.com
Table 6-40. Switching Characteristics Over Recommended Operating Conditions in Video Display Mode
for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx⁽¹⁾⁽²⁾
(see Figure 6-24)
NO.
PARAMETER
-720
-900
MIN
MAX
UNIT
1 t_c(VKO)
Cycle time, VPxCLKOUTx
V – 0.7 V + 0.7 ns
2 t_w(VKOH)
Pulse duration, VPxCLKOUTx high
VH – 0.7 VH + 0.7 ns
3 t_w(VKOL)
Pulse duration, VPxCLKOUTx low
VL – 0.7 VL + 0.7 ns
4 t_t(VKO)
5 t_d(VKIH-VKOH)
6 t_d(VKIL-VKOL)
Transition time, VPxCLKOUTx
Delay time, VPxCLKINx high to VPxCLKOUTx high⁽³⁾
Delay time, VPxCLKINx low to VPxCLKOUTx low⁽³⁾
1.8 ns
1.1
5.7 ns
1.1
5.7 ns
7 t_d(VKIH-VKOL)
Delay time, VPxCLKINx high to VPxCLKOUTx low
1.1
5.7 ns
8 t_d(VKIL-VKOH)
9 t_{d(VKIH-VPOUTV)}
10 t_{d(VKIH-VPOUTIV)}
11 t_{d(VKOH-VPOUTV)}
12 t_{d(VKOH-VPOUTIV)}
Delay time, VPxCLKINx low to VPxCLKOUTx high
Delay time, VPxCLKINx high to VPxOUT valid⁽⁴⁾
Delay time, VPxCLKINx high to VPxOUT invalid⁽⁴⁾
Delay time, VPxCLKOUTx high to VPxOUT valid⁽¹⁾⁽⁴⁾
Delay time, VPxCLKOUTx high to VPxOUT invalid⁽¹⁾⁽⁴⁾
1.1
5.7 ns
9 ns
1.7
ns
4.3 ns
–0.2
ns
(1) V = the video input clock (VPxCLKINx) period in ns.
(2) VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns.
(3) Assuming non-inverted VPxCLKOUTx signal.
(4) VPxOUT consists of VPxCTLx and VPxD[19:0]
VPxCLKINx
VPxCLKOUTx
[VCLK2P = 0]
5
2
1
3
6
VPxCLKOUTx
(Inverted)
[VCLK2P = 1]
4
7
11
4
8
12
VPxCTLx,V
PxD[19:0]
(Outputs)
9
15
10
16
VPxCTLx
(Input)
14
13
Figure 6-24. Video Port Display Data Output Timing and Control Input/Output Timing With Respect to
VPxCLKINx and VPxCLKOUTx
108 Peripheral Information and Electrical Specifications
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