ADS62P45_08 Datasheet, PDF (55/70 Pages) Texas Instruments – DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

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ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561A – JULY 2007 – REVISED FEBRUARY 2008
It is also possible to freeze the offset correction using the serial interface (<OFFSET LOOP FREEZE>). Once
frozen, the offset estimation becomes inactive and the last estimated value is used for correction every clock
cycle. Note that the offset correction is disabled by default after reset.
Figure 99 shows the time response of the offset correction algorithm, after it is enabled.
8260
8240
8220
8200
Device With
Offset Cancelled
8180
8160
8140
Offset Loop
Enabled Here
Device With
Initial Offset
8120
0
2
4
6
8
10 12 14
t − Time − s
G084
Figure 99. Time Response of Offset Correction
Gain Correction
ADS62P4X has ability to make fine corrections to the ADC channel gain. The corrections can be done in steps of
0.05 dB, up to a maximum of 0.5 dB, using the register bits (GAIN CORRECTION). Only positive corrections are
supported and the same correction applies to both the channels.
Table 21. Gain Correction Values
<GAIN CORRECTION>
D3-D2-D1-D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Other combinations
AMOUNT OF CORRECTION,
dB
0
+0.05
+0.1
+0.15
+0.20
+0.25
+0.30
+0.35
+0.40
+0.45
+0.5
Unused
Copyright © 2007–2008, Texas Instruments Incorporated
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