ADS62P45_08 Datasheet, PDF (41/70 Pages) Texas Instruments – DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

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ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561A – JULY 2007 – REVISED FEBRUARY 2008
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f_I − Input Frequency − MHz
Figure 81. ADC Analog Bandwidth
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G080
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection. A 5-Ω resistor in series with each input pin is recommended
to damp out ringing caused by the package parasitics.
It is also necessary to present low impedance (50 Ω) for the common mode switching currents. This can be
achieved by using two resistors from each input terminated to the common mode voltage (VCM).
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. While doing this, the ADC input impedance must be considered.
Figure 82 and Figure 83 show the impedance (Zin = Rin || Cin) looking into the ADC input pins.
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f − Frequency − MHz
G081
Figure 82. ADC Analog Input Resistance (Rin) Across Frequency
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