ADS62P45_08 Datasheet, PDF (38/70 Pages) Texas Instruments – DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561A – JULY 2007 – REVISED FEBRUARY 2008
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TYPICAL CHARACTERISTICS - LOW SAMPLING FREQUENCIES
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 V_PP differential clock amplitude, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
100
95
90
85
80
75
70
0
F_S = 25 MSPS
SFDR vs INPUT FREQUENCY
80
78
Gain = 3.5 dB
76
74
72
Gain = 0 dB
70
68
25 50 75 100 125 150 175 200
f_IN − Input Frequency − MHz
G075
Figure 75.
66
0
SNR vs INPUT FREQUENCY
Gain = 0 dB
Gain = 3.5 dB
25 50 75 100 125 150 175 200
f_IN − Input Frequency − MHz
G076
Figure 76.
COMMON PLOTS
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 V_PP differential clock amplitude, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
COMMON-MODE REJECTION RATIO vs FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
25 50 75 100 125 150 175 200
f − Frequency − MHz
G077
Figure 77.
POWER DISSIPATION vs
SAMPLING FREQUENCY (DDR LVDS and CMOS)
1.0
0.9 ^{fIN = 2.5 MHz}
C_L = 5 pF
0.8
0.7
LVDS
0.6
0.5
0.4
CMOS
0.3
0.2
0.1
0.0
0
25
50
75
100
125
f_S − Sampling Frequency − MSPS
G078
Figure 78.
38
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