ADS62P45_08 Datasheet, PDF (17/70 Pages) Texas Instruments – DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

www.ti.com
ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561A – JULY 2007 – REVISED FEBRUARY 2008
Table 9.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
12
0
0
<LVDS TERMINATION> Internal termination programmability
D5–D3
000
001
010
011
100
101
110
111
D2–D0
000
001
010
011
100
101
110
111
<LVDS DATA TERM> Internal termination control for data outputs
No internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
<LVDS CLK TERM> Internal termination control for clock output
No internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
A7–A0
(hex)
13
D4
0
1
Table 10.
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
<OFFSET FREEZE>
0
0
0
0
<OFFSET FREEZE> Offset correction becomes inactive and the last estimated offset value is used to cancel the offset
Offset correction active
Offset correction inactive
Copyright © 2007–2008, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42