ADS6225 Datasheet, PDF (53/75 Pages) Texas Instruments – DUAL CHANNEL, 12-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE

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ADS6225, ADS6224
ADS6223, ADS6222
SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007
Input Clock,
CLK
Freq = Fs
Frame Clock,
FCLK
Freq = 1 ´ Fs
Bit Clock,
DCLK
Freq = 6 ´ Fs
Output Data
DA, DB, DC, DD
Data Rate = 12 ´ Fs
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10
(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9) (D10) (D11) (D0) (D1)
Bit Clock,
DCLK
Freq = 7 ´ Fs
Output Data
DA, DB, DC, DD
Data Rate = 14 ´ Fs
0
0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9) (D10) (D11) (0)
D0 0
0
(0) (D0) (D1)
Sample N
Sample N + 1
Data Bit in MSB First Mode
D13
(D2)
Data Bit in LSB First Mode
(1) _{In 14-Bit serialization, two zero bits are padded to the 12-bit ADC data on the MSB side.}
T0225-01
Figure 91. 1-Wire Interface
2-WIRE INTERFACE – 12× SERIALIZATION WITH DDR/SDR BIT CLOCK
The 2-wire interface is recommended for sampling frequencies above 65 MSPS. The device outputs the data of
each ADC serially on two LVDS pairs (2-wire). The data rate is 6 × Sample frequency since 6 bits are sent on
each wire every clock cycle. The data is available along with DDR bit clock or optionally with SDR bit clock. Each
ADC sample is sent over the 2 wires as byte-wise or bit-wise or word-wise.
Copyright © 2007, Texas Instruments Incorporated
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