ADS6225 Datasheet, PDF (1/75 Pages) Texas Instruments – DUAL CHANNEL, 12-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE

ADS6225, ADS6224
ADS6223, ADS6222
www.ti.com
SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007
DUAL CHANNEL, 12-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE
FEATURES
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• Maximum Sample Rate: 125 MSPS
• 12-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5 dB Coarse Gain and up to 6 dB
Programmable Fine Gain for SFDR/SNR
Trade-Off
• Serialized LVDS Outputs with Programmable
Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS Clock
Inputs and Amplitude Down to 400 mV_pp
• Internal Reference with External Reference
Support
• No External Decoupling Required for
References
• 3.3-V Analog and Digital Supply
• 48 QFN Package (7 mm × 7 mm)
• Pin Compatible 14-Bit Family (ADS624X -
SLAS542)
• Feature Compatible Quad Channel Family
(ADS644X - SLAS531 and ADS642X - SLAS532)
APPLICATIONS
• Base-Station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment
Table 1. ADS62XX Dual Channel Family
ADS624X
14 Bit
ADS622X
12 Bit
125 MSPS 105 MSPS 80 MSPS 65 MSPS
ADS6245 ADS6244 ADS6243 ADS6242
ADS6225 ADS6224 ADS6223 ADS6222
Table 2. Performance Summary
SFDR, dBc
Fin = 10MHz (0 dB gain)
Fin = 170MHz (3.5 dB gain)
Fin = 10MHz (0 dB gain)
SINAD, dBFS
Fin = 170MHz (3.5 dB gain)
Power per channel, mW
ADS6225
90
79
70.7
67.4
500
ADS6224
91
81
70.8
68.1
405
ADS6223
91
82
71.3
68.2
350
ADS6222
93
83
71.3
68.7
315
DESCRIPTION
ADS6225/ADS6224/ADS6223/ADS6222 (ADS622X) is a family of high performance 12-bit 125/105/80/65 MSPS
dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a
compact 48-pin QFN package (7 mm × 7 mm) that allows for high system integration density. The device
includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in
SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1 dB steps up to 6 dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it
possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing
receiver design. The ADS622X also includes the traditional 1-wire interface that can be used at lower sampling
frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit
clock is used to serialize the ADC data from each channel. In addition to the serial data streams, the frame and
bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable
LVDS currents, current doubling modes and internal termination options. These can be used to widen
eye-openings and improve signal integrity, easing capture by the receiver.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated