ADS6225 Datasheet, PDF (26/75 Pages) Texas Instruments – DUAL CHANNEL, 12-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE

ADS6225, ADS6224
ADS6223, ADS6222
SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007
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PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued)
NAME
PINS
NO.
NO.
I/O OF
PINS
DESCRIPTION
SCLK
This pin functions as serial interface clock input when RESET is low.
34
I
1
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along
with SDATA). See Table 5 for description.
This pin has an internal pull-down resistor.
SDATA
This pin functions as serial interface data input when RESET is low.
33
I
1
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along
with SCLK). See Table 5 for description.
This pin has an internal pull-down resistor.
SEN
This pin functions as serial interface enable input when RESET is low.
32
I
1
When RESET is high, it controls coarse gain and internal/external reference modes. See
Table 6 for description.
This pin has an internal pull-up resistor.
Serial interface reset input.
RESET
When using the serial interface mode, the user MUST initialize internal registers through
4
I
1
hardware RESET by applying a high-going pulse on this pin or by using software reset option.
Refer to the Serial Interface section. In parallel interface mode, tie RESET permanently high.
(SCLK, SDATA and SEN function as parallel control pins in this mode).
The pin has an internal pull-down resistor to ground.
PDNA
31
I 1 Channel A ADC power down control pin.
PDNB
30
I 1 Channel B ADC power down control pin.
CFG1
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection. See
23
I 1 Table 9 for description.
Tie to ground for 1-wire interface with DDR bit clock.
CFG2
Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture edge. See
22
I 1 Table 10 for description.
For 12x serialization with DDR bit clock, tie to ground or AVDD.
CFG3
21
I 1 RESERVED pin - TIE to ground.
CFG4
15
I
1
Parallel input pin. It controls data format and MSB or LSB first modes. See Table 12 for
description.
VCM
Internal reference mode – common-mode voltage output
16
IO 1 External reference mode – reference input. The voltage forced on this pin sets the internal
reference.
OUTPUT PINS
DA_P,DA_M
45,46 O 2 Channel A differential LVDS data output pair
DB_P,DB_M
39,40 O 2 Channel B differential LVDS data output pair
DCLKP,DCLKM 43,44 O 2 Differential bit clock output pair
FCLKP,FCLKM
41,42
O 2 Differential frame clock output pair
UNUSED
37,38,47,4
8
4 These pins are unused in the 1-wire interface. Do not connect
NC
14
1 Do not connect
PAD
0
1
Connect to ground plane using multiple vias. Refer to Board Design Considerations in
application section
26
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