TMS320DM647_09 Datasheet, PDF (52/181 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009
TC0
TC1
TC2
TC3
Megamodule
HPI
PCI
VLYNQ
Ethernet Subsystem
Table 4-1. Connectivity Matrix for Data SCR
MEGAMODULE DDR2 EMIF EMIFA VIDEO
VIDEO
PCI
PORT 0-2 PORT 3-4
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
N
N
Y
Y
Y
Y
N
N
Y
Y
Y
Y
N
N
Y
Y
Y
Y
N
N
N
www.ti.com
VLYNQ
Y
Y
Y
N
Y
Y
Y
Y
N
Configuration
SCR
Y
Y
Y
N
N
Y
Y
Y
N
4.3 Configuration Switch Fabric
Figure 4-2 shows the connection between the C64x+ megamodule and the configuration SCR, which is
mainly used by the C64x+ Megamodule to access peripheral registers. The data SCR also has a
connection to the configuration SCR that allows masters to access most peripheral registers. The only
registers not accessible by the data SCR through the configuration SCR are the device configuration
registers and the PLL1 and PLL2 controller registers; these can be accessed only by the C64x+
Megamodule. The configuration SCR uses 32-bit configuration buses running at SYSCLK1 frequency.
SYSCLK1 is supplied by the PLL1 controller and is fixed at a frequency equal to the CPU frequency
divided by 3.
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System Interconnect
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