TMS320DM647_09 Datasheet, PDF (27/181 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
www.ti.com
SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009
TERMINAL NAME
VP2D13/VRXD1
VP2D14/VRXD2
VP2D15/VRXD3
VP2D16/VTXD0
VP2D17/VTXD1
VP2D18/VTXD2
VP2D19/VTXD3
VP3CLK0/ AECLKIN
VP3CLK1/
AECLKOUT
VP3CTL0/
AAWE/ASWE
VP3CTL1/ AR/W
VP3CTL2/
AAOE/ASOE
VP3D02/AED00
VP3D03/AED01
VP3D04/AED02
VP3D05/AED03
VP3D06/AED04
VP3D07/AED05
VP3D08/AED06
VP3D09/AED07
VP3D12/AED08
VP3D13/AED09
VP3D14/AED10
VP3D15/AED11
VP3D16/AED12
VP3D17/AED13
VP3D18/AED14
VP3D19/AED15
VP4CLK0/AARDY
VP4CLK1
VP4CTL0/ABA0
VP4CTL1/ABA1
Table 2-4. Terminal Functions (continued)
NO TYPE
V3 I/O/Z
V4 I/O/Z
U1 I/O/Z
U3 I/O/Z
U2 I/O/Z
U5 I/O/Z
U4 I/O/Z
T1
I
P1 I/O/Z
INTERNAL
PULLUP/
PULLDOWN
OPER DESCRIPTION
VOLT
IPD
3.3 V Video Port 2 Data 13 or VLYNQ receive data pin [1] (I)
IPD
3.3 V Video Port 2 Data 14 or VLYNQ receive data pin [2] (I)
IPD
3.3 V Video Port 2 Data 15 or VLYNQ receive data pin [3] (I)
IPD
3.3 V Video Port 2 Data 16 or VLYNQ transmit data pin [0] (O)
IPD
3.3 V Video Port 2 Data 17 or VLYNQ transmit data pin [1] (O)
IPD
3.3 V Video Port 2 Data 18 or VLYNQ transmit data pin [2] (O)
IPD
3.3 V Video Port 2 Data 19 or VLYNQ transmit data pin [3] (O)
VIDEO PORT 3 OR EMIFA
IPD
3.3 V Video Port 3 Clock 0 (I) or EMIFA external input clock (I)
IPD
3.3 V Video Port 3 Clock 1 or EMIFA output clock (O/Z)
T2 I/O/Z
R1 I/O/Z
P2 I/O/Z
T6 I/O/Z
T5 I/O/Z
T4 I/O/Z
T3 I/O/Z
R6 I/O/Z
R5 I/O/Z
R4 I/O/Z
R3 I/O/Z
R2 I/O/Z
P6 I/O/Z
P5 I/O/Z
P4 I/O/Z
P3 I/O/Z
N4 I/O/Z
N6 I/O/Z
N5 I/O/Z
L1
I
K1 I/O/Z
J2 I/O/Z
J1 I/O/Z
IPU
3.3 V Video Port 3 Control 0 or Asynchronous memory write
enable/Programmable synchronous interface write-enable
IPU
3.3 V Video Port 3 Control 1 or Asynchronous memory read/write (O/Z)
IPU
3.3 V Video Port 3 Control 2 or Asynchronous/Programmable
synchronous memory output-enable (O/Z)
IPU
3.3 V Video Port 3 Data 2 or EMIFA External Data 0
IPU
3.3 V Video Port 3 Data 3 or EMIFA External Data 1
IPU
3.3 V Video Port 3 Data 4 or EMIFA External Data 2
IPU
3.3 V Video Port 3 Data 5 or EMIFA External Data 3
IPU
3.3 V Video Port 3 Data 6 or EMIFA External Data 4
IPU
3.3 V Video Port 3 Data 7 or EMIFA External Data 5
IPU
3.3 V Video Port 3 Data 8 or EMIFA External Data 6
IPU
3.3 V Video Port 3 Data 9 or EMIFA External Data 7
IPU
3.3 V Video Port 3 Data 12 or EMIFA External Data 8
IPU
3.3 V Video Port 3 Data 13 or EMIFA External Data 9
IPU
3.3 V Video Port 3 Data 14 or EMIFA External Data 10
IPU
3.3 V Video Port 3 Data 15 or EMIFA External Data 11
IPU
3.3 V Video Port 3 Data 16 or EMIFA External Data 12
IPU
3.3 V Video Port 3 Data 17 or EMIFA External Data 13
IPU
3.3 V Video Port 3 Data 18 or EMIFA External Data 14
IPU
3.3 V Video Port 3 Data 19 or EMIFA External Data 15
VIDEO PORT 4 OR EMIFA
IPU
3.3 V Video Port 4 Clock 0 (I) or Asynchronous memory ready input (I)
IPD
3.3 V Video Port 4 Clock 1
IPD
3.3 V Video Port 4 Control 0 or EMIFA bank address control (ABA[1:0])
(O/Z). Active-low bank selects for the 16-bit EMIFA. When
interfacing to 16-bit asynchronous devices, ABA1 carries bit 1 of
the byte address. For an 8-bit asynchronous interface, ABA[1:0]
are used to carry bits 1 and 0 of the byte address.
IPD
3.3 V Video Port 4 Control 1 or EMIFA bank address control (ABA[1:0])
(O/Z). Active-low bank selects for the 16-bit EMIFA. WHEN
interfacing to 16-bit asynchronous devices, ABA1 carries bit 1 of
the byte address. For an 8-bit asynchronous interface, ABA[1:0]
are used to carry bits 1 and 0 of the byte address.
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