TMS320DM647_09 Datasheet, PDF (164/181 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009
www.ti.com
Table 6-81. Ethernet Subsystem Timing Requirements (continued)
PARAMETER ⁽¹⁾
MIN
NOM
MAX
t₀₂ REFCLKP/N duty cycle
t₀₃ REFCLKP/N rise/fall
t₀₄ PLL Clock Period, x n Mode
t₀₅ PLL power up
40
60
700
t₀₁ / n
1 + 200 * C
UNITS
%
ps
ns
ms
REFCLKP/N Jitter and PLL Loop Bandwidth
Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby
impairing system performance. A good quality, low jitter reference clock is necessary to achieve
compliance with most if not all physical layer standards (see Table 6-82).
Table 6-82. REFCLKP/N Jitter Requirements for Standards Compliance
Standard
Gigabit Ethernet
Line Rate (Gbps)
1.25
Total REFCLKP/N Jitter (within PLL bandwidth)
50 ps pk-pk
164 Peripheral Information and Electrical Specifications
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