TMS320DM647_09 Datasheet, PDF (42/181 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009
www.ti.com
3.2.4 Priority Allocation (PRI_ALLOC)
Each of the masters (excluding the C64x+ Megamodule) is assigned a priority via the Priority Allocation
Register (PRI_ALLOC), see Figure 3-4. The priority is enforced when several masters in the system are
vying for the same endpoint. A value of 000b has the highest priority, while 111b has the lowest priority.
Note that the configuration SCR port on the data SCR is considered a single endpoint meaning priority will
be enforced when multiple masters try to access the configuration SCR. Priority is also enforced on the
configuration SCR side when a master (through the data SCR) tries to access the same endpoint as the
C64x+ Megamodule.
The Ethernet Subsystem and VLYNQ fields specify the priority of the Ethernet Subsystem and VLYNQ
peripherals, respectively. Similarly, the HOST field applies to the priority of the HPI and PCI peripherals.
Other master peripherals are not present in the PRI_ALLOC register as they have their own registers to
program their priorities. For more information on the default priority values in these peripheral registers,
see the device-compatible peripheral reference guides.
TI recommends that these priority registers be reprogrammed during device initialization.
MASTER
EDMA3TC0
EDMA3TC1
EDMA3TC2
EDMA3TC3
64x+_DMAP
64x+_CFGP
Ethernet Subsystem
VLYNQ
UHPI
PCI
VICP
Table 3-6. Default Master Priorities
DEFAULT PRIORITY
0 (EDMA CC QUEPRI Register)
0 (EDMA CC QUEPRI Register)
0 (EDMA CC QUEPRI Register)
0 (EDMA CC QUEPRI Register)
7 (C64x+ MDMAARBE.PRI Register bit field)
1 (C64x+ MDMAARBE.PRI Register bit field)
3 (PRI_ALLOC register)
4 (PRI_ALLOC register)
4 (PRI_ALLOC register)
4 (PRI_ALLOC register)
5 (PRI_ALLOC register)
Figure 3-4. Priority Allocation Register (PRI_ALLOC)
31
Reserved
R-0000000000001000
15
12
11
9
8
6
Reserved
VICP
VLYNQ
R-0000
R/W-101
R/W-100
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
5
3
HOST
R/W-100
16
2
0
Ethernet Subsystem
R/W-011
42
Device Configuration
Copyright © 2010–2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320DM647 TMS320DM648