THS8136 Datasheet, PDF (5/17 Pages) Texas Instruments – TRIPLE 10-BIT 180-MSPS GRAPHICS AND VIDEO DAC

THS8136
www.ti.com ........................................................................................................................................................................................... SLES236 – NOVEMBER 2008
Blanking Generation
The BLANK control input forces the output amplitude on all channels to the blanking or reference level,
irrespective of the value on the data input ports. The output blanking level on each channel and its relation to
active video varies depending on the mode of operation. In generic DAC mode, the output blank level for each
DAC is at 0 V and corresponds to a DAC input code of 0. When sync insertion is enabled a 350-mV dc bias (R_FS
selected for 700-mV output) is applied to provide room for bi-level sync insertion. When RGB sync insertion is
enabled, the output blank level of each DAC will be at 350 mV and will correspond to a DAC input code of 0. In
YPbPr video mode, the blank level of each DAC is 350 mV, but the AR and AB blank levels correspond to a DAC
input code of 512 to accommodate mid-level UV blank levels. A video to blank level amplitude ratio of 2:1 is
maintained for various R_FS values, provided the maximum DAC output compliance is not exceeded.
Sync Generation
The SYNC and SYNC_T control inputs can be used to enable the superposition of a bi-level sync on the AG
DAC output. Correctly timed assertion of the SYNC input (active low) allows insertion of an analog composite
sync on the AG DAC output consisting of horizontal sync and vertical sync. The video to sync amplitude ratio is
7:3 providing a 300 mV sync tip, when FSADJ is selected to provide 700 mV full-scale graphics or video. This
7:3 video to sync amplitude ratio is maintained for various R_FS values, provided the maximum DAC output
compliance is not exceeded. The SYNC-T input pin must be connected to DV_SS (or logic low) to enable sync
insertion.
Device Configuration
The THS8136 operating mode is determined from the state of the SYNC, SYNC-T, M1, and M2 control terminals.
Generic DAC mode is easily selected by connecting SYNC and SYNC_T to DV_DD (or logic high) and M1 and M2
to DV_SS (logic low). To enable sync insertion, the SYNC_T terminal must be connected to DVSS (or logic low).
YPbPr video mode can be selected for support of mid-level PbPr blanking by connecting the sync control input to
both the SYNC and M2 input terminals. The M1 terminal must be connected to DV_SS (logic 0) for all operating
modes. See Table 1 and Figure 4, Figure 5, and Figure 6 for additional information on configuring the THS8136.
OPERATING MODE M1
Generic DAC
0
RGB Sync Insertion
0
YPbPr Sync Insertion
0
Table 1. Table 1. Device Configuration
M2
0
0
SYNC
SYNC_T
1
0
0
SYNC
1
SYNC
SYNC
DESCRIPTION
Sync insertion disabled. The blank level on all DAC outputs corresponds
to 0-V and DAC input code 0.
DC bias and sync insertion enabled. The blank level on all DAC outputs
corresponds to DAC input code 0.
DC bias and sync insertion enabled. AB and AR mid-level blanking
corresponds to DAC input code 512.
DAC Operation
The DAC output drivers generate a current with a drive level that can be user-modified by choosing an
appropriate resistor value R_FS connected between the FSADJ terminal and AV_SS (GND). All current source
amplitudes (graphics/video, blanking, and sync on AG) are derived from R_FS and an internal voltage reference
such that the relative amplitudes of sync, blank, and graphics/video are always equal to their nominal
relationships. The relative amplitudes of these current drivers are maintained without regard to the value of R_FS,
as long as the maximum current drive capability is not exceeded. Figure 3 shows the relationship between R_FS
and the current drive level on each channel for full-range DAC input. The voltage compliance outputs in Figure 3
assume termination with a 37.5-Ω resistor. When sync insertion is enabled, an additional current source is
enabled providing a DC bias and head-room for negative sync insertion. A fixed R_FS value of 3.8 kΩ (R_FS(nom)) is
suitable for most applications requiring 700-mV output levels.
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS8136
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