THS8136 Datasheet, PDF (11/17 Pages) Texas Instruments – TRIPLE 10-BIT 180-MSPS GRAPHICS AND VIDEO DAC

THS8136
www.ti.com ........................................................................................................................................................................................... SLES236 – NOVEMBER 2008
ANALOG (DAC) OUTPUTS ELECTRICAL CHARACTERISTICS
over recommended operating conditions, f_CLK = 180 MHz, use of internal reference voltage V_REF, R_FS = R_FS(nom),
37.5-Ω load termination (unless otherwise noted)
INL
DNL
PSRR
V_refo
R_R
K_IMBAL
V_OC
I_FS
t_RDAC
t_FDAC
t_d(A)
t_S
PARAMETER
TEST CONDITIONS
DAC resolution
Integral nonlinearity
Static, best fit, RGB with sync insertion (700 +
sync)
Static, best fit, generic mode, 1.2 V output range
Differential nonlinearity
Static, RGB with sync insertion (700 + sync)
Static, generic mode, 1.2 V output range
Power supply ripple rejection ratio of
DAC output (full scale)
f = DC⁽¹⁾
Voltage reference output
V_REF output resistance
Imbalance between DACs⁽²⁾
CLK = 80 MSPS, video mode
DAC output compliance voltage
Generic DAC mode
RGB with sync insertion enabled
DAC output current rise time
DAC output current fall time
CLK = 80 MSPS⁽³⁾
CLK = 80 MSPS⁽³⁾
CLK = 80 MSPS, 10 to 90% of full scale⁽⁴⁾
CLK = 80 MSPS, 10 to 90% of full scale⁽⁴⁾
Analog output delay
Measured from CLK = V_IH(min) to 50% of
full-scale transition⁽⁵⁾
Analog output settling time
Measured from 50% of full scale transition on
output to output settling, within 2%⁽⁴⁾
MIN
1.12
–2
18
27
2.8
2.8
TYP MAX UNIT
10
Bits
-1/1 –2.5/1.5
LSB
–1/1
–0.4/0.4
-0.4/0.4
±1
LSB
38.5
dB
1.16
284
1.8
0.7
18.67
28
3.3
3.3
1.20 V
Ω
2%
1.2 V
19.5
mA
29.3
3.6 ns
3.6 ns
4.5
ns
15
ns
(1) PSRR is measured with a 0.1-µF capacitor between the COMP and AV_DD pins and with a 0.1-µF capacitor connected between the V_REF
and AV_SS pins. The ripple amplitude is within the range 100 mVp-p to 500 mVp-p with the DAC output set to full scale and a
double-terminated 75 Ω (= 37.5 Ω) load. PSRR is defined as 20 × log(ripple voltage at DAC output/ripple voltage at AV_DD input). Limits
are from characterization only.
(2) The imbalance between DACs applies to all possible pairs of the three DACs.
(3) Values at R_FS = R_FS(nom)
(4) From characterization only. Measured on the AG channel with R_FS = R_FS(nom).
(5) This value excludes the digital process delay, t_D(D). Limit are from characterization only.
Copyright © 2008, Texas Instruments Incorporated
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