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THS8136 Datasheet, PDF (3/17 Pages) Texas Instruments – TRIPLE 10-BIT 180-MSPS GRAPHICS AND VIDEO DAC
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THS8136
www.ti.com ........................................................................................................................................................................................... SLES236 – NOVEMBER 2008
TERMINAL FUNCTIONS
TERMINAL
I/O
NAME
NO.
DESCRIPTION
AB
45
O Analog blue current output, capable of directly driving a double terminated 75-Ω coaxial cable
AG
41
O Analog green current output, capable of directly driving a double terminated 75-Ω coaxial cable
AR
43
O Analog red current output, capable of directly driving a double terminated 75-Ω coaxial cable
AVDD
AVSS
SYNC
40, 44 I Analog power supply (3.3 V). All AVDD pins must be connected.
42, 46 I Analog ground
24
I Sync insertion input. Active low. When asserted, the G output is forced to the bottom sync tip level.
SYNC-T
25
I
Connect to DVSS (GND) or logic low to enable bi-level sync insertion. Connect to DVDD (1.8 V) or logic high
for generic DAC applications not requiring sync insertion.
M2
48
I
Connect to DVSS (GND) or logic 0 for RGB blanking level operation. Connect to the SYNC control input for
YPbPr video operation.
M1
47
I Must be tied to DVSS (GND) or logic 0 for normal operation.
B0
10
B1
9
B2
8
B3
7
B4
B5
6
5
I
Blue or (Pb) pixel data input. Signals with index 0 denote the least significant bit. Unused inputs should be
connected to DVSS(GND).
B6
4
B7
3
B8
2
B9
1
BLANK
23
I
Blanking control input, active low. A rising edge on CLK latches BLANK. When asserted, the AR, AG, and AB
outputs are driven to the reference blanking level, regardless of the value on the data inputs.
CLK
26
I Clock input. A rising edge on CLK latches R0–R9, G0–G9, B0–B9, and BLANK.
COMP
DVDD
DVSS
FSADJ
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
39
O Compensation terminal. A 0.1-µF capacitor must be connected between COMP and AVDD.
12
I Digital power supply (1.8 V)
11
I Digital ground
Full-scale adjust control. The full-scale current drive on each of the output channels is determined by the
38
I value of a resistor RFS connected between this terminal and AVSS. Figure 3 shows the relationship between
full-scale output voltage compliance and RFS for the nominal DAC termination of 37.5 Ω.
36
35
34
33
32
31
I
Green (or Y) pixel data input. Signals with index 0 denote the least significant bit. Unused inputs should be
connected to DVSS(GND).
30
29
28
27
R0
13
R1
14
R2
15
R3
16
R4
R5
17
18
I
Red (or Pr) pixel data input. Signals with index 0 denote the least significant bit. Unused inputs should be
connected to DVSS(GND).
R6
19
R7
20
R8
21
R9
22
Copyright © 2008, Texas Instruments Incorporated
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