DS90CR213_05 Datasheet, PDF (5/15 Pages) Texas Instruments – 21-Bit Channel Link-66 MHz

Receiver Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min Typ Max Units
RSKM
RxIN Skew Margin (Note 7) V _CC = 5V,T_A = 25˚C(Figure 17) f = 40 MHz
700
ps
f = 66 MHz
600
ps
RCOP
RxCLK OUT Period (Figure 7 )
15
T
50
ns
RCOH
RxCLK OUT High Time (Figure 7 )
f = 40 MHz
6
ns
f = 66 MHz
4.3
5
ns
RCOL
RxCLK OUT Low Time (Figure 7 )
f = 40 MHz
10.5
ns
f = 66 MHz
7.0
9
ns
RSRC
RxOUT Setup to RxCLK OUT (Figure 7 )
f = 40 MHz
4.5
ns
f = 66 MHz
2.5
4.2
ns
RHRC
RxOUT Hold to RxCLK OUT (Figure 7 )
f = 40 MHz
6.5
ns
f = 66 MHz
4
5.2
ns
RCCD
RPLLS
RxCLK IN to RxCLK OUT Delay @25˚C, V_CC = 5.0V (Figure 9 )
Receiver Phase Lock Loop Set (Figure 11 )
6.4
10.7
ns
10
ms
RPDD
Receiver Powerdown Delay (Figure 15 )
1
µs
Note 7: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
01288803
01288802
01288804
FIGURE 2. DS90CR213 (Transmitter) LVDS Output Load and Transition Times
5
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