DS90CR213_05 Datasheet, PDF (12/15 Pages) Texas Instruments – 21-Bit Channel Link-66 MHz

Applications Information (Continued)
the design considerations discussed here and listed in the
supplemental application notes provide the subsystem com-
munications designer with many useful guidelines. It is rec-
ommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.
BOARD LAYOUT
To obtain the maximum benefit from the noise and EMI
reductions of LVDS, attention should be paid to the layout of
differential lines. Lines of a differential pair should always be
adjacent to eliminate noise interference from other signals
and take full advantage of the noise canceling of the differ-
ential signals. The board designer should also try to maintain
equal length on signal traces for a given differential pair. As
with any high speed design, the impedance discontinuities
should be limited (reduce the numbers of vias and no 90
degree angles on traces). Any discontinuities which do occur
on one signal line should be mirrored in the other line of the
differential pair. Care should be taken to ensure that the
differential trace impedance match the differential imped-
ance of the selected physical media (this impedance should
also match the value of the termination resistor that is con-
nected across the differential pair at the receiver’s input).
Finally, the location of the CHANNEL LINK TxOUT/RxIN pins
should be as close as possible to the board edge so as to
eliminate excessive pcb runs. All of these considerations will
limit reflections and crosstalk which adversely effect high
frequency performance and EMI.
UNUSED INPUTS
All unused inputs at the TxIN inputs of the transmitter must
be tied to ground. All unused outputs at the RxOUT outputs
of the receiver must then be left floating.
TERMINATION
Use of current mode drivers requires a terminating resistor
across the receiver inputs. The CHANNEL LINK chipset will
normally require a single 100Ω resistor between the true and
complement lines on each differential pair of the receiver
input. The actual value of the termination resistor should be
selected to match the differential mode characteristic imped-
ance (90Ω to 120Ω typical) of the cable. Figure 18 shows an
example. No additional pull-up or pull-down resistors are
necessary as with some other differential technologies such
as PECL. Surface mount resistors are recommended to
avoid the additional inductance that accompanies leaded
resistors. These resistors should be placed as close as
possible to the receiver input pins to reduce stubs and
effectively terminate the differential lines.
DECOUPLING CAPACITORS
Bypassing capacitors are needed to reduce the impact of
switching noise which could limit performance. For a conser-
vative approach three parallel-connected decoupling capaci-
tors (Multi-Layered Ceramic type in surface mount form fac-
tor) between each V_CC and the ground plane(s) are
recommended. The three capacitor values are 0.1 µF,
0.01µF and 0.001 µF. An example is shown in Figure 19. The
designer should employ wide traces for power and ground
and ensure each capacitor has its own via to the ground
plane. If board space is limiting the number of bypass ca-
pacitors, the PLL V_CC should receive the most filtering/
bypassing. Next would be the LVDS V_CC pins and finally the
logic V_CC pins.
FIGURE 18. LVDS Serialized Link Termination
01288824
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