DS90CR213_05 Datasheet, PDF (10/15 Pages) Texas Instruments – 21-Bit Channel Link-66 MHz

AC Timing Diagrams (Continued)
FIGURE 16. Transmitter LVDS Output Pulse Position Measurement
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SW — Setup and Hold Time (Internal Data Sampling Window)
TCCS — Transmitter Output Skew
RSKM ≥ Cable Skew (Type, Length) + Source Clock Jitter (Cycle to Cycle)
Cable Skew — Typically 10 ps–40 ps per foot
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FIGURE 17. Receiver LVDS Input Skew Margin
DS90CR213 Pin Description—Channel Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
I/O No.
Description
I
21 TTL level inputs.
O
3 Positive LVDS differential data output.
O
3 Negative LVDS differentiaI data output.
I
1 TTL level clock input. The rising edge acts as data strobe.
O
1 Positive LVDS differential clock output.
O
1 Negative LVDS differential clock output.
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