DS90CR213_05 Datasheet, PDF (4/15 Pages) Texas Instruments – 21-Bit Channel Link-66 MHz

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Units
TRANSMITTER SUPPLY CURRENT
Power Down
Driver Outputs in TRI-STATE under
Powerdown Mode
1
25
µA
RECEIVER SUPPLY CURRENT
I_CCRW
Receiver Supply Current
Worst Case
C_L = 8 pF,
Worst Case Pattern
f = 32.5 MHz
f = 37.5 MHz
64
77
mA
70
85
mA
(Figure 1 and Figure 3 ) f = 66 MHz
110
140
mA
I_CCRZ
Receiver Supply Current
Power Down
Powerdown = Low
Receiver Outputs in Previous State during
Power Down Mode.
1
10
µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 5.0V and T_A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V_OD and ∆V _OD).
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
PLL V_CC ≥ 1000V
All Other Pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Note 5: V_OS previously referred as V_CM.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
LLHT LVDS Low-to-High Transition Time (Figure 2 )
LHLT LVDS High-to-Low Transition Time (Figure 2 )
TCIT
TxCLK IN Transition Time (Figure 4 )
TCCS TxOUT Channel-to-Channel Skew (Note 6) (Figure 5)
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 16 )
−0.30
TPPos1 Transmitter Output Pulse Position for Bit 1
1.70
TPPos2 Transmitter Output Pulse Position for Bit 2
3.60
TPPos3 Transmitter Output Pulse Position for Bit 3
f = 66 MHz 5.90
TPPos4 Transmitter Output Pulse Position for Bit 4
8.30
TPPos5 Transmitter Output Pulse Position for Bit 5
10.40
TPPos6 Transmitter Output Pulse Position for Bit 6
12.70
TCIP
TxCLK IN Period (Figure 6 )
15
TCIH
TxCLK IN High Time (Figure 6 )
0.35T
TCIL
TxCLK IN Low Time (Figure 6 )
0.35T
TSTC TxIN Setup to TxCLK IN (Figure 6 )
5
THTC TxIN Hold to TxCLK IN (Figure 6 )
2.5
TCCD TxCLK IN to TxCLK OUT Delay @25˚C, V_CC = 5.0V (Figure 8 )
3.5
TPLLS Transmitter Phase Lock Loop Set (Figure 10 )
TPDD Transmitter Powerdown Delay (Figure 14 )
Note 6: This limit based on bench characterization.
Typ
0.75
0.75
0
(1/7)Tclk
(2/7)Tclk
(3/7)Tclk
(4/7)Tclk
(5/7)Tclk
(6/7)Tclk
T
0.5T
0.5T
3.5
1.5
Max
1.5
1.5
8
350
0.30
2.50
4.50
6.75
9.00
11.10
13.40
50
0.65T
0.65T
8.5
10
100
Units
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min Typ Max Units
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 3 )
2.5
4.0
ns
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 3 )
2.0
4.0
ns
www.national.com
4