DS16EV5110SQ Datasheet, PDF (5/24 Pages) Texas Instruments – DS16EV5110 Video Equalizer (3D+C) for DVI, HDMI Sink-Side Applications

DS16EV5110
www.ti.com
SNLS249M – FEBRUARY 2007 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.⁽¹⁾⁽²⁾
Symbol
Parameter
Conditions
Min
N
Supply Noise Tolerance ⁽³⁾
DC to 50MHz
CML INPUTS
V_TX
Input Voltage Swing (Launch
Amplitude)
Measured differentially at TPA
(Figure 2)
800
V_ICMDC
Input Common-Mode Voltage
DC-Coupled Requirement
Measured at TPA (Figure 2)
V_DD-0.3
V_IN
Input Voltage Swing
Measured differentially at TPB
(Figure 2)
R_LI
Differential Input Return Loss
100 MHz– 825 MHz, with fixture's
effect de-embedded
R_IN
Input Resistance
CML OUTPUTS
IN+ to VDD and IN− to VDD
45
V_O
Output Voltage Swing
Measured differentially with OUT+
and OUT− terminated by 50Ω to
800
VDD
V_OCM
t_R, t_F
Output common-mode Voltage
Transition Time
Measured Single-ended
20% to 80% of differential output
voltage, measured within 1" from
output pins.
V_DD-0.3
75
t_CCSK
Inter Pair Channel-to-Channel
Skew (all 4 Channels)
Difference in 50% crossing
between shortest and longest
channels
t_D
Latency
OUTPUT JITTER
TJ1
Total Jitter at 1.65 Gbps
20m 28 AWG STP DVI Cable
Data Paths
EQ Setting 0x04 PRBS7^{(4) (5) (6)}
TJ2
Total Jitter at 2.25 Gbps
20m 28 AWG STP DVI Cable
Data Paths
EQ Setting 0x04 PRBS7^{(4) (5) (6)}
TJ3
Total Jitter at 165 MHz
Clock Paths
Clock Pattern^{(4) (5) (6)}
TJ4
Total Jitter at 225 MHz
RJ
Random Jitter
Clock Paths
Clock Pattern^{(4) (5) (6)}
See ^{(6) (7)}
BIT RATE
F_CLK
BR
Clock Frequency
Bit Rate
Clock Path⁽⁴⁾
Data Path⁽⁴⁾
25
0.25
Typ
100
120
10
50
25
350
0.13
0.2
0.165
3
Max
1200
V_DD-0.2
55
1200
V_DD-0.2
240
0.17
0.165
225
2.25
Units
mV_P-P
mV_P-P
V
mV_P-P
dB
Ω
mV_P-P
V
ps
ps
ps
UI_P-P
UI_P-P
UI_P-P
UI_P-P
ps_rms
MHz
Gbps
(3) Allowed supply noise (mV_P-P sine wave) under typical conditions.
(4) Specification is ensured by characterization and is not tested in production.
(5) Deterministic jitter is measured at the differential outputs (TPC of Figure 2), minus the deterministic jitter before the test channel (TPA of
Figure 2). Random jitter is removed through the use of averaging or similar means.
(6) Total Jitter is defined as peak-to-peak deterministic jitter from ⁽⁾ + 14.2 times random jitter in ps_rms.
(7) Random jitter contributed by the equalizer is defined as sq rt (J_OUT2 − J_IN2). J_OUT is the random jitter at equalizer outputs in ps_rms, see
TPC of Figure 2; J_IN is the random jitter at the input of the equalizer in ps_rms, see TPA of Figure 2.
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